Abstract: An MOS gate turn-off thyristor structure includes non-regenerative (three-layer or transistor) portions interspersed with the four-layer regenerative (thyristor) portions and further includes gate electrode segments disposed adjacent to relatively narrow portions of the base region. Upon application of an appropriate turn-off gate bias to the gate electrode segments, the base region of the regenerative portion in which they are disposed is pinched off and the current flowing therethrough is diverted to flow through the non-regenerative portion of the structure. This interrupts regeneration in the regenerative structure and the device turns off.

Abstract: A semiconductor device comprising a bulk substrate and an epitaxial layer grown thereon attains the feature of rapid removal of majority carriers from an N-type active base region thereof, a function conventionally performed by anode shorts, through the incorporation into the otherwise P-type substrate of a highly doped, N-type region having a surface in contact with the N-type epitaxial layer for injecting majority carriers from an N-type active base region in the epitaxial layer into the remaining P-type portion of the substrate.

Abstract: An insulated-gate semiconductor device includes an IGFET with channel, base, drift and drain regions, and further includes source and drain electrodes attached to at least the base region and to the drain region, repectively. The device further includes a carrier injection region which adjoins the IGFET drift region and forms a P-N junction therewith. Biasing structure connected to the carrier injection region and effective during the on-state of the device is provided for forward biasing the P-N junction by an amount sufficient to induce injection of carriers from the carrier injection region, across the P-N junction, and into the IGFET drift region. As a consequence, the on-resistance of the device is markedly reduced.

Abstract: An eight mask process for forming a lateral insulated gate semiconductor device is disclosed. The gate structure can be used as a mask to align the third and fifth regions of the device and a third protective layer aligns the fourth and sixth regions of the device.

Abstract: A solid state composite control circuit includes a normally-off gating device connected in series with a normally-on high voltage semiconductor device so that the combination operates as a normally-off high power semiconductor device. The control device is a low voltage semiconductor device, which can switch rapidly with very low gate turn-off current during turn-off of the composite circuit. In a particular example, a low voltage, normally-off, MOSFET is connected in series with the cathode of a high voltage, normally-on FCT. In another example, a low voltage, normally-off, MOSFET is connected in series with the source of a high voltage, normally-on JFET. The composite circuit has a very high turn-off gain as well as high dv/dt and di/dt capability.

Abstract: A semiconductor device incorporates a JFET serially connected to a bipolar transistor to achieve normally-off operation. An impedance element is connected between the base of the bipolar transistor and the gate of the JFET, which serves as a single control electrode for the entire device. When a current is supplied to the control electrode, the bipolar transistor and JFET are both switched to the on state. In the JFET, the P-N junction between the gate region and the channel region is sufficiently forward-biased so as to inject current carriers into its channel region and markedly reduce the device on-resistance. An electrical circuit analogue of the device achieves the advantage of low on-resistance and normally-off operation.

Abstract: A high speed semiconductor pinch rectifier attains low forward voltage drop and low reverse leakage current by utilizing depletion region pinch-off of conduction channels in a high-resistivity region. In a preferred form, the pinch rectifier additionally utilizes a Schottky barrier contact so as to facilitate device fabrication.

Abstract: Reduction in the forward current gain of an inherent bipolar transistor in an insulated-gate semiconductor device such as an IGT or an IGFET is achieved by implantation of selected ions into the semiconductor material of such device. The ions, which create defects in the implanted region constituting current carrier recombination centers, form a layer with a peak concentration situated in proximity to the emitter-base junction of the inherent bipolar transistor. The layer of ions is of small thickness, whereby the resulting increase in the respective sheet resistances of the emitter and base layers to either side of the emitter-base junction is minimized.

Abstract: Hybrid power switching semiconductor devices advantageously integrate IGT and MOSFET structures. The IGT and MOSFET portions of the overall device include respective gate structures each having an associated gate electrode capacitance, and the hybrid device includes a resistance element connecting the IGT and MOSFET gates. The gate structures preferably comprise polysilicon electrodes, and the resistance element comprises a polysilicon bridge formed at the same time during device fabrication. The overall device has only a single gate terminal, which is connected relatively directly to one of the IGT and MOSFET gates, and indirectly through the resistance element to the other of the IGT and MOSFET gates such that an RC time delay network is defined. Two different types of power switching functions are achieved depending upon whether the overall device gate terminal is connected nearer the IGT gate or the MOSFET gate.

Abstract: A vertical channel junction gate electric field controlled device (e.g., a field effect transistor, or a field controlled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves, generally on the upper surface of the base region layer, are upper electrode regions, for example, source electrode regions or cathode electrode regions. Recessed in the grooves are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions in the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection.

Abstract: A vertical channel junction gate electric field controlled device (e.g., a field effect transistor or a field controlled thyristor) includes a semiconductor base region layer, and a plurality of grooves having vertical walls formed in the upper surface of the base region layer. Between the grooves on the upper surface of the base region layer but not extending to the grooves are upper electrode regions, for example, source electrode regions or cathode electrode regions. Formed in the groove bottoms and sidewalls are junction gate regions. Upper electrode terminal metallization is evaporated generally on the upper device layer, and gate terminal metallization is over the junction gate regions at the bottoms of the grooves. The disclosed structure thus has continuous metallization along the recessed gate regions for a low-resistance gate connection.

Abstract: Gate turn-off field controlled thyristors having high forward blocking capabilities and high blocking gains, and planar, junction gate field effect transistors having high source-to-drain breakdown voltage capability with high differential blocking gain, include a gate region having a plurality of vertical-walled grooves. The devices are fabricated by preferentially etching one surface of a semiconductor substrate, selectively refilling the grooves with a vapor phase epitaxial growth, forming a plurality of first electrode regions on the same surface and interdigitated with the gate region, and forming a second electrode region on the opposite surface of the substrate.

Abstract: An improved semiconductor device having a diffused region of reduced length and an improved method of fabricating such a semiconductor device are disclosed. The semiconductor device may be a MOSFET or an IGR, by way of example. In a form of the method of fabricating a MOSFET, an N.sup.+ SOURCE is diffused into a P BASE through a window of a diffusion mask. An anisotropic or directional etchant is applied to the N.sup.+ SOURCE through the same window. The etchant removes most of the N.sup.+ SOURCE, but allows shoulders thereof to remain intact. These shoulders, which form the completed N.sup.+ SOURCE regions, are of reduced length, greatly reducing the risk of turn-on of a parasitic bipolar transistor in the MOSFET. The risk of turn-on of a parasitic bipolar transistor in an IGR is similarly reduced, when the IGR is fabricated by the improved method.

Abstract: Inversion-mode insulated field-effect transistor structures are provided wherein a lightly-doped GaAs drift or drain region is combined with a gate-controlled channel structure comprising a film or layer of a semiconductor layer other than GaAs and within which inversion regions may more readily be formed. Suitable semiconductor materials for the gate-controlled channel structure are InP and Ga.sub.x In.sub.1-x As. Presently preferred is a Ga.sub.x In.sub.1-x As graded layer wherein x ranges from 1.0 to about 0.47.

Abstract: An electrical circuit includes a JFET serially connected to an IGFET, the gate of the IGFET constituting the gate for the circuit. Biasing structure, such as a resistor, is connected between the circuit gate and the gate of the JFET for forward-biasing the P-N junction of the JFET extant between its gate and channel regions. When this P-N junction is biased by more than about 0.6 volts for a silicon JFET, the JFET gate region injects current carriers into the JFET channel region, whereby bipolar conduction occurs in the JFET channel region and low on-resistance for the circuit is achieved. In a preferred circuit the biasing structure comprises an IGFET, which advantageously results in the circuit gate having a high input impedance.

Abstract: A semiconductor device incorporates a JFET serially connected to a bipolar transistor to achieve normally-off operation. An impedance element is connected between the base of the bipolar transistor and the gate of the JFET, which serves as a single control electrode for the entire device. When a current is supplied to the control electrode, the bipolar transistor and JFET are both switched to the on state. In the JFET, the p-N junction between the gate region and the channel region is sufficiently forward-biased so as to inject current carriers into its channel region and markedly reduce the device on-resistance. An electrical circuit analogue of the device achieves the advantage of low on-resistance and normally-off operation.

Abstract: Methods for fabricating vertical channel buried grid field controlled devices with improved performance characteristics include methods which avoid the problems caused by autodoping effects. In one form of the invention, one surface of a semiconductor substrate is preferentially etched to form substantially vertically-walled grooves, and the grooves are selectively refilled employing vapor phase epitaxial growth to form a grid structure. A semiconductor layer is then epitaxially grown over the substrate surface and grid so as to bury the grid. In another form of the invention, grooves are preferentially etched in semiconductor substrate to achieve steep vertical walls. Thereafter, the grooves are either partially refilled by means of epitaxial growth or, preferably, completely refilled and then again preferentially etched to remove a predetermined fraction of the refilling. A second epitaxial refill is done to fill the remainder of the grooves.

Abstract: A semiconductor device, such as a MOSFET or IGR, is fabricated with a base region having a deep portion for reducing parasitic currents. A wafer is provided having an N type layer on an appropriately doped substrate. A first oxide layer is formed on the wafer, and a refractory electrode layer is deposited on the first oxide layer. A first window is opened in the refractory electrode layer, and then silicon nitride is deposited on the wafer. A second window is opened in the silicon nitride layer, within the first window. A deep P.sup.+ base region is diffused into the wafer through the second window, and then a second oxide layer is selectively grown in the second window. The silicon nitride layer is selectively removed, thereby opening a third window, defined by the second window and the second oxide layer situated within the second window. A shallow P base region is diffused into the wafer through the third window, followed by diffusion of a shallow N.sup.+ region through the third window.

Abstract: Improved high frequency GaAs FETs have a higher breakdown voltage, lower input gate capacitance and lower source (or drain) resistance. A preferentially etched groove structure yields parallel trapezoidal semiconductor fingers that are wider at the top than at the bottom. Every finger intersects a high resistivity, semi-insulating region which surrounds the active device area and is fabricated by high energy particle bombardment. Metal gates are deposited within the grooves on three sides of the trapezoidal fingers.

Abstract: A high frequency field effect transistor of gallium arsenide or other III-V semiconductor compounds has a preferentially etched trapezoidal groove structure in the top surface which creates parallel trapezoidal semiconductor fingers that are wider at the top than at the bottom. Schottky gates or junction gates are fabricated within the grooves surrounding the elongated fingers. The vertical conducting channels between the gates are narrow leading to a high blocking gain, and more contact area is available at the top of the device.