Patents by Inventor Bao G. Truong

Bao G. Truong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7607028
    Abstract: A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: October 20, 2009
    Assignee: International Business Machines Corporation
    Inventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao G. Truong, Roger D. Weekly
  • Publication number: 20090113107
    Abstract: A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.
    Type: Application
    Filed: January 7, 2009
    Publication date: April 30, 2009
    Applicant: International Business Machines Corporation
    Inventors: Anand Haridass, Bao G. Truong, Joel D. Ziegelbein
  • Publication number: 20090094307
    Abstract: Performing a calculation using a coordinate rotation digital computer (CORDIC) algorithm. Execution of the CORDIC algorithm is begun. An error introduced by a truncated vector as a result of executing the CORDIC algorithm is pre-computed. The error is incorporated into a subsequent iteration of the CORDIC algorithm. Execution of the CORDIC algorithm is completed. The result of the CORDIC algorithm is stored.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Inventors: David N. Ault, Emiliano Lozano, Bao G. Truong, Samuel I. Ward
  • Patent number: 7512183
    Abstract: A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: March 31, 2009
    Assignee: International Business Machines Corporation
    Inventors: Anand Haridass, Bao G. Truong, Joel D. Ziegelbein
  • Publication number: 20090048794
    Abstract: A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
    Type: Application
    Filed: October 30, 2008
    Publication date: February 19, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao G. Truong, Roger D. Weekly
  • Patent number: 7477068
    Abstract: A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
    Type: Grant
    Filed: March 29, 2008
    Date of Patent: January 13, 2009
    Assignee: International Business Machines Corporation
    Inventors: Bao G. Truong, Daniel Mark Dreps, Anand Haridass, John C. Schiff, Joel D. Ziegelbein
  • Publication number: 20090013227
    Abstract: A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test vector. The method further comprises operating a random pattern generator to generate data blocks, each corresponding to one of the test vectors, wherein the data block corresponding to a given test vector is encoded with a bit pattern representing the coding scheme of the given test vector. The corresponding data block also has a bit length that is less than the bit length of the given test vector. Each data block is routed to at least one of a plurality of decoders, wherein each decoder is adapted to recognize the coding scheme represented by one of the bit patterns.
    Type: Application
    Filed: July 5, 2007
    Publication date: January 8, 2009
    Inventors: Gahn W. Krishnakalin, Emiliano Lozano, Bao G. Truong, Samuel I. Ward
  • Patent number: 7468929
    Abstract: A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed is provided. Logic is provided that identifies a polarity of a row of memory cells whose data values are to be read. The polarity of the row of memory cells indicates whether a majority of the data values stored in the row of memory cells are logic 1 data values or logic 0 data values. Based on the polarity, selection logic either selects true data values or complement data values of the memory cells. Additional logic is provided in each memory cell for outputting a true data value to a read bit line and outputting a compliment data value to the read bit line based on the polarity.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: December 23, 2008
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Lee, Bao G. Truong
  • Patent number: 7469199
    Abstract: An apparatus and method are provided for monitoring the voltage available in each domain of multiple voltage domains of a partitioned electronic chip. The apparatus comprises a single conductive link coupled to the chip, and further comprises a domain selection network having a single output and a plurality of switchable inputs, the output being connected to the single conductive link, and two inputs being connected to monitor respective voltage levels of two of the plurality of voltage domains. A control mechanism is disposed to operate the selection network, in order to selectively connect one of the inputs to the single conductive link, and a sensor device external to the electronic chip is connected to measure the monitored respective voltage levels of two of the plurality of voltage domains using the single conductive link.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: December 23, 2008
    Assignee: International Business Machines Corporation
    Inventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao G. Truong, Roger D. Weekly
  • Patent number: 7467050
    Abstract: A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: December 16, 2008
    Assignee: International Business Machines Corporation
    Inventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao G. Truong, Roger D. Weekly
  • Patent number: 7430800
    Abstract: A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: October 7, 2008
    Assignee: International Business Machines Corporation
    Inventors: Anand Haridass, Andreas Huber, Bao G. Truong, Roger D. Weekly
  • Publication number: 20080175327
    Abstract: A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
    Type: Application
    Filed: March 29, 2008
    Publication date: July 24, 2008
    Applicant: International Business Machines Corporation
    Inventors: Bao G. Truong, Daniel Mark Dreps, Anand Haridass, John C. Schiff, Joel D. Ziegelbein
  • Patent number: 7391231
    Abstract: An active terminator is configured with switches to select between terminating two lines for transmitting one differential signal pair or two single ended signals terminated in a pseudo-differential receiver. The receiver circuitry is configured with three differential comparators. One differential comparator receives both signal lines and other two differential comparators each receive one signal line and a reference voltage. The signal lines are terminated in a resistive voltage divider with electronic switches coupling the positive and ground voltages. The top and bottom nodes of the resistor divider in both terminators are cross-coupled with pass gates. In the pseudo-differential mode the pass gates are OFF and the electronic switches are ON with known resistances. In the differential mode, the electronic switches are OFF and the pass gates are ON with known resistances. The pass gate and switch resistances are sized with the resistors to insure a desired termination impedance.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: June 24, 2008
    Assignee: International Business Machines Corporation
    Inventors: Carlos I. Gomez, Bao G. Truong
  • Publication number: 20080143375
    Abstract: A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
    Type: Application
    Filed: December 15, 2006
    Publication date: June 19, 2008
    Inventors: Bao G. Truong, Daniel Mark Dreps, Anand Haridass, John C. Schiff, Joel D. Ziegelbein
  • Publication number: 20080140925
    Abstract: An apparatus and method for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or “no-hit” situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 12, 2008
    Inventors: MICHAEL J. LEE, Bao G. Truong
  • Publication number: 20080137450
    Abstract: A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed are provided. Logic is provided for determining the polarity of an incoming row being written to the SRAM cell array. Logic is further provided for storing a polarity value into an additional SRAM cell per row of the SRAM cell array. Logic is also provided for reading an inverted value of the SRAM cells of a row in the SRAM cell array if the row contains more 0's than 1's, as determined based on the polarity value stored in the additional SRAM cell per row. Logic is further provided for signaling to downstream logic whether the data read from the SRAM cells in the row represents the true data values or their complement, as determined based on the polarity value stored in the additional SRAM cell per row.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 12, 2008
    Inventors: Michael J. Lee, Bao G. Truong
  • Publication number: 20080140924
    Abstract: An apparatus and method for transparent multi-hit correction in associative memories are provided. In one illustrative embodiment, a content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 12, 2008
    Inventors: MICHAEL J. LEE, Vinod Ramadurai, Bao G. Truong
  • Patent number: 7382151
    Abstract: A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: June 3, 2008
    Assignee: International Business Machines Corporation
    Inventors: Bao G. Truong, Daniel Mark Dreps, Anand Haridass, John C. Schiff, Joel D. Ziegelbein
  • Publication number: 20070290712
    Abstract: An active terminator is configured with switches to select between terminating two lines for transmitting one differential signal pair or two single ended signals terminated in a pseudo-differential receiver. The receiver circuitry is configured with three differential comparators. One differential comparator receives both signal lines and other two differential comparators each receive one signal line and a reference voltage. The signal lines are terminated in a resistive voltage divider with electronic switches coupling the positive and ground voltages. The top and bottom nodes of the resistor divider in both terminators are cross-coupled with pass gates. In the pseudo-differential mode the pass gates are OFF and the electronic switches are ON with known resistances. In the differential mode, the electronic switches are OFF and the pass gates are ON with known resistances. The pass gate and switch resistances are sized with the resistors to insure a desired termination impedance.
    Type: Application
    Filed: June 19, 2006
    Publication date: December 20, 2007
    Inventors: Carlos I. Gomez, Bao G. Truong
  • Publication number: 20070288182
    Abstract: A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
    Type: Application
    Filed: May 30, 2006
    Publication date: December 13, 2007
    Inventors: Daniel Douriet, Anand Haridass, Andreas Huber, Colm B. O'Reilly, Bao G. Truong, Roger D. Weekly