Abstract: A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.

Abstract: A receiver circuit is configured as a frequency compensated differential amplifier having one input coupled to the output of a transmission line to receive a transmitted signal and the second input coupled to a reference voltage. The differential amplifier has a high frequency gain equivalent to the gain of an uncompensated differential stage for the transmitted signal. The compensated differential amplifier has an attenuated low frequency gain for signal frequencies substantially lower than the high frequency and a transitional gain for frequencies between the low and high frequencies. A compensated stage provides the portion of the signal with a compensated response and an uncompensated stage provides the portion of the amplified signal that is uncompensated. Bias control signals determine how much of the output signal is from the compensated and uncompensated stages as a means for customizing response from transmission lines with varying losses.

Abstract: A reference generator circuit has a resistor string between the potentials of the power supply voltage that is partitioned into a top string, a middle string, and a bottom string. PFET devices are used to couple the positive power supply voltage a selected node of the top string in response to first control signals and complementary second control signals are used to control NFET devices that couple the ground power supply voltage to a selected node of the bottom string. If a resistor is effectively removed from the top string a corresponding resistor is effectively added in the bottom string keeping the total resistance in the resistor string substantially constant. A pass gate network is used to select between nodes of the middle string as a vernier for generating small step sizes.

Abstract: Signaling between two or more ICs use a signaling scheme wherein a reference signal is generated at the driver side and the receiver side. The driver side reference signal is coupled to the receiver side reference signal with a transmission line channel forming a reference channel. Data signal channels are paired with a reference channel between each two adjacent data channels. Adjacent pairs of data signal channels are each separated with an empty wiring channel. The paired data signals are received in one input of a differential receiver. The reference signal of the reference channel between the two paired data channels is coupled to the other input of the two differential receivers. Coupling from the paired data channels to the reference channel appears a common mode noise and is rejected by the differential receivers. The number of channels is reduced from a full differential signaling scheme.

Abstract: Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an N×1 MUX. The N×1 MUX is controlled by the skew controller. The output of the N×1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.

Abstract: Two or more integrated circuit (IC) chips are separated by a significant distance relative to their communication frequency such that pseudo-differential signaling is used to improve signal detection. A derived reference voltage is generated that tracks the variations of the driver and receiver side power supply variations that normally reduce noise margins. The derived reference voltage is filtered to reduce high frequency response and coupled as the reference to differential receivers used to detect the logic levels of the communication signals.