Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a first movable portion, a fixed portion, a first driving assembly, and a first guiding assembly. The first movable portion is used for connecting to a first optical element driving mechanism. The first optical element driving mechanism has a main axis that extends in a first direction. The first movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the first movable portion to move relative to the fixed portion. The first guiding assembly is used for guiding the movement of the fixed portion relative to the fixed portion.

Abstract: This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.

Abstract: A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.

Abstract: An optical element drive mechanism is provided. The optical element drive mechanism includes an immovable part, a first movable part, a first drive assembly, and a guidance assembly. The first movable part is movable relative to the immovable part. The first movable part is connected to a first optical element. The first drive assembly drives the first movable part to move relative to the immovable part. The guidance assembly guides the movement of the first movable part in the first dimension.

Abstract: A speaker module is adapted to be configured to a wearable device. The speaker module includes an enclosure and a driving unit. The driving unit is used to generate sound. The enclosure contains the driving unit. A sound sum of the sound output from a front opening, a first rear opening and a second rear opening of the enclosure has directivity. The connection vectors and the inverse vector of the connection normal vector defined by these openings are added to form a combined vector. A unit vector of the combination vector and a unit vector of a front normal vector facing outwards of the front opening are added to form a sum vector. The direction of the sum vector is the direction of the sound sum.

Abstract: A data storage system with intelligent power management includes a plurality of data storage devices and a controller. Each data storage device is capable of operating in one of (N+1) power saving functions where N is an integer larger than 1. The (N+1) power saving functions sequentially correspond to from the 0th to the Nth power saving levels. The controller reads a user-setting power saving level (I) where I is an integer index ranging from 0 to N. The controller reads a current power saving level (J) of a current power saving function of one of the plurality of data storage devices where J is an integer index ranging from 0 to N. The controller controls said one data storage device to operate in one power saving function among the (N+1) power saving functions according to the user-setting power saving level (I) and the current power saving level (J).

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.

Abstract: An ultra-large height top electrode for MRAM is achieved by employing a novel thin metal/thick dielectric/thick metal hybrid hard mask stack. Etching parameters are chosen to etch the dielectric quickly but to have an extremely low etch rate on the metals above and underneath. Because of the protection of the large thickness of the dielectric layer, the ultra-large height metal hard mask is etched with high integrity, eventually making a large height top electrode possible.

Abstract: This disclosure provides for robust isolation across the SOI structure. In contrast to forming a charge trap layer in specific areas on the structure, a charge trap layer may be built across the insulating/substrate interface. The charge trap layer may be an implantation layer formed throughout and below the insulation layer. Devices built on this SOI structure have reduced cross-talk between the devices. Due to the uniform structure, isolation is robust across the structure and not confined to certain areas. Additionally, deep trench implantation is not required to form the structure, eliminating cost. The semiconductor-on-insulator substrate may include an active silicon layer over an oxide layer. The oxide layer may be over a charge trap layer. The charge trap layer may be over a silicon substrate.

Abstract: A method of forming a semiconductor device includes providing a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.

Abstract: An optical system is provided. The optical system includes an immovable part, a second movable part, a second drive mechanism, and a second circuit mechanism. The second movable part is used for connecting to a second optical element. The second movable part is movable relative to the immovable part. The second drive mechanism is used for driving the second movable part to move relative to the immovable part. The second circuit mechanism is electrically connected to the second drive mechanism.

Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

Abstract: An optical system, disposed on an electrical device, including a movable portion, a connected portion, and a driving assembly. The movable portion is connected to an optical module. The connected portion connects the movable portion to the electrical device. The driving assembly drives the movable portion to move relative to the electrical device.

Abstract: In certain embodiments, a system includes: a source lane configured to move a first die container between a load port and a source lane staging area; an inspection sensor configured to produce a sensor result based on a die on the first die container; a pass target lane configured to move a second die container between a pass target lane out port and a pass target lane staging area; a fail target lane configured to move a third die container between a fail target lane out port and a fail target lane staging area; and a conveyor configured to move the die from the first die container at the source lane staging area to either the second die container at the pass target lane staging area or the fail target lane staging area based on the sensor result.

Abstract: A semiconductor device according to the present disclosure includes a first conductive feature and a second conductive feature in a first dielectric layer, a buffer layer over the first dielectric layer, a second dielectric layer over the buffer layer, a first bottom via extending through the buffer layer and the second dielectric layer, a second bottom via extending through the buffer layer and the second dielectric layer, a first bottom electrode disposed on the first bottom via, a second bottom electrode disposed on the second bottom via, a first magnetic tunnel junction (MTJ) stack over the first bottom electrode, and a second MTJ stack over the second bottom electrode. The first MTJ stack and the second MTJ stack have a same thickness. The first MTJ stack has a first width and the second MTJ stack has a second width greater than the first width.

Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Abstract: Semiconductor-on-insulator (SOI) field effect transistors (FETs) including body regions having different thicknesses may be formed on an SOI substrate by selectively thinning a region of a top semiconductor layer while preventing thinning of an additional region of the top semiconductor layer. An oxidation process or an etch process may be used to thin the region of the top semiconductor layer, and a patterned oxidation barrier mask or an etch mask may be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. Shallow trench isolation structures may be formed prior to, or after, the selective thinning processing steps. FETs having different depletion region configurations may be formed using the multiple thicknesses of the patterned portions of the top semiconductor layer. For example, partially depleted SOT FETs and fully depleted SOI FETs may be provided.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.

Abstract: A pancake lens assembly includes a partially reflective mirror, a reflective polarizer, a quarter waveplate, a polarization-dependent optical device, and at least one polarization controller. When a light beam is introduced into the pancake lens assembly along an optical axis in a Z direction to pass through the polarization controller in a first state, a polarization direction of the light beam is converted by the polarization controller. When the light beam is introduced into the pancake lens assembly along the optical axis to pass through the polarization controller in a second state, the polarization direction of the light beam is prevented from being converted by the polarization controller.

Abstract: An optical system is provided, including a movable part, a fixed part, a first sensor, a second sensor, and a control unit, wherein an optical element is disposed on the movable part. The first and second sensors detect the movement of the movable part relative to the fixed part in a first dimension and a second dimension, and thus they respectively generate a first sensing value and a second sensing value. The control unit generates an error value according to the first sensing value and an error curve, and then calibrates the second sensing value according to the error value.