Abstract: A transceiver used in a communications system includes a transmitter having a transmit input that is split into a transmit I component and a transmit Q component; a receiver having a receive input that is split into a receive I component and a receive Q component; a switching network configured to input the transmit I component, the transmit Q component, the receive I component and the receive Q component; and to output a sampled sequence; an analog to digital converter configured to receive the sampled sequence and to output a digitized data stream; and a digital signal processor configured to receive the digitized data stream and process the digitized data stream.

Abstract: A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same.

Abstract: A multistandard RF transceiver is disclosed that may optionally include selectable mixers; selectable amplifiers; a configurable analog filter; and a configurable analog to digital converter. The multistandard RF transceiver may also include a data interface for sending data to a host controller and a control interface for receiving configuration commands from the host controller. The configuration commands identify a wireless standard that is to be implemented by the RF receiver. An RF processor processes an RF signal wherein the processed RF signal is output to the host controller on the data interface.

Abstract: A power amplifier comprises an amplification stage comprises a plurality of amplifiers, wherein each amplifier provides an amplified output, and an inductive summing device configured to receive the plurality of amplified outputs and provide a combined output signal. A method of amplifying a signal comprises applying the signal to an amplifier stage comprising a plurality of amplifiers, wherein each amplifier is configured to provide an amplified output, and providing a combined output signal via an inductive summing device configured to receive the plurality of amplified outputs.

Abstract: A system and method are disclosed for configuring a frequency synthesizer in a transceiver. Configuring a frequency synthesizer in a transceiver includes specifying a selection bit sequence wherein the selection bit sequence corresponds to a predetermined combination of transceiver characteristics; determining a plurality of synthesizer configuration parameters using the selection bit sequence; and configuring the frequency synthesizer using the plurality of synthesizer configuration parameters.

Abstract: A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.

Abstract: A phase synchronous multiple LC tank oscillator is described. A plurality of oscillator stages are configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same and the plurality of oscillators are inductively coupled.

Abstract: A multistandard RF transceiver is disclosed that may optionally include selectable mixers; selectable amplifiers; a configurable analog filter; and a configurable analog to digital converter. The multistandard RF transceiver may also include a data interface for sending data to a host controller and a control interface for receiving configuration commands from the host controller. The configuration commands identify a wireless standard that is to be implemented by the RF receiver. An RF processor processes an RF signal wherein the processed RF signal is output to the host controller on the data interface.

Abstract: A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages that are configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same and the plurality of oscillators are inductively coupled. The synchronous oscillation is substantially caused by magnetic coupling. The oscillator stages may be electrically coupled during a first time period and the electrical coupling and disconnected or reduced during a second time period.

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

Abstract: A communication transmitting and receiving system in which the effects of near-end echo and near-end crosstalk signal from the communication medium are mitigated by adaptively reproducing the near-end echo and near-end crosstalk signal, which is then subtracted from the received signal. Filter coefficients for a Finite Impulse Response filter are adaptively generated to reproduce the near-end echo and near-end crosstalk. The filter coefficients are regenerated for the Finite Impulse Response filter in an adaptive correlator at the arrival of each received signal and whereby each new filter coefficient is a weighted sum of a previous coefficient and one received signal multiplied by a time delayed version of one transmitted signal.

Abstract: A phase synchronous multiple LC tank oscillator includes a plurality of oscillator stages configured to oscillate synchronously. The phase of each of the plurality of oscillator stages is substantially the same.

Abstract: A system and method are disclosed for generating a synthesized signal. A frequency synthesizer is used. The frequency synthesizer includes an input interface configured to receive an input signal having a reference frequency; a phase locked loop (PLL) coupled to the input interface, having a fractional N configuration and comprises a voltage controlled oscillator; wherein the voltage controlled oscillator is configured to generate the synthesized signal; and the voltage controlled oscillator includes an on-chip inductor.

Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: A system and method are disclosed for generating a variable frequency output. A voltage controlled oscillator (VCO) is used. The VCO comprises a plurality of aggregate capacitor circuits, wherein each of the aggregate capacitor circuits has a collective capacitance, at least two of the collective capacitances have different values, and each of the aggregate capacitor circuits includes one or more individual capacitors wherein each of the individual capacitors are substantially the same size. The VCO further comprises a plurality of switches configured to select one or more aggregate capacitor circuits from among the plurality of aggregate capacitor circuits to form a discretely variable capacitor network having a discretely variable capacitance, wherein the discretely variable capacitor network is configured to cause an oscillator to generate a variable frequency as a result of the discretely variable capacitance.

Abstract: A system and method are disclosed for generating a synthesized signal. A frequency synthesizer is used. The frequency synthesizer includes an input interface configured to receive an input signal having a reference frequency; a phase locked loop (PLL) coupled to the input interface, having a fractional N configuration and comprises a voltage controlled oscillator; wherein the voltage controlled oscillator is configured to generate the synthesized signal; and the voltage controlled oscillator includes an on-chip inductor.

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: A system and method are disclosed for providing a FSK demodulator using DLL and a demodulating method which detects a time order of the rising edges of square waves that correspond to two modulation frequencies and an in-between frequency and demodulates the relevant frequencies into data. The FSK demodulator includes a band-pass filter, an amplitude limiter for converting a waveform of the frequency filtered into a square wave, a delay line for receiving the square wave from the amplitude limiter and delaying the square wave for a delay time, a delayed flip-flop (DFF) for receiving an output signal from the amplitude limiter and an output signal from the delay line, determining which rising edge of the two input signals is earlier at a given time, and outputting the result of the determination as data, and a DLL circuit that locks the delay time of the delay line.