Abstract: A storage medium includes at least one data unit defining a plurality of symbol-based inner code words and a plurality of symbol-based outer code words. Each symbol included in one of the inner code words is also included in one of the outer code words. A processor is configured to perform a first iteration of inner code error correction on the plurality of symbol-based inner code words, a first iteration of outer code error correction on the plurality of symbol-based outer code words and a second iteration of inner code error correction on the plurality of symbol-based inner code words. In the first iteration of outer code error corrections, at least one of the outer code words is correctable. In the second iteration of inner code error correction, at least one of the inner code words is correctable.

Abstract: A nominal reference read operation compares analog voltages of the memory cells to at least one nominal reference voltage. A shifted reference read operation compares the analog voltages of the memory cells to at least one shifted reference voltage that is shifted from the nominal reference voltage to compensate for an expected change in the analog voltages of the memory cells. Data stored in the memory cells is decoded by a first decoding process that uses the information from either the nominal reference read operation or the shifted reference read operation. The data stored in the memory cells is decoded by a second decoding process that uses the information from both the nominal reference read operation and the shifted reference read operation.

Abstract: Various approaches that reduce the width variability of storage media data tracks are described. First and second data tracks are written so that the second track overlaps the first track. After writing the second track data to the second track, an effective width of the first track is determined. The effective width of the first track is the portion of the first track that is not overlapped by the second track. One or more additional write operations to the recording medium are performed to compensate for the effective width of the first track being less than a threshold. The additional write operations may include one or more of rewriting the first track data to a third track on the storage medium and writing additional redundancy information to supplement the coding of the first track data.

Abstract: A first write request that is associated with a first logical address is received via a collection of write requests targeted to a non-volatile, solid state memory. It is determined whether the logical address is related to logical addresses of one or more other write requests of the collection that are not proximately ordered with the first write request in the collection. In response to this determination, the first write request and the one or more other write requests are written together to the memory.

Abstract: Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.

Abstract: A nominal reference read operation compares analog voltages of the memory cells to at least one nominal reference voltage. A shifted reference read operation compares the analog voltages of the memory cells to at least one shifted reference voltage that is shifted from the nominal reference voltage to compensate for an expected change in the analog voltages of the memory cells. Data stored in the memory cells is decoded by a first decoding process that uses the information from either the nominal reference read operation or the shifted reference read operation. The data stored in the memory cells is decoded by a second decoding process that uses the information from both the nominal reference read operation and the shifted reference read operation.

Abstract: This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.

Abstract: At least two groupings are established for a plurality of erase units. The erase units include flash memory units that are available for writing subsequent to erasure. The groupings are based at least on a recent write frequency of data targeted for writing to the erase units. A wear criteria is determined for each of the erase units and the erase units are assigned to one of the respective groupings based on the wear criteria of the respective erase units and further based on a wear range assigned to each of the at least two groupings.

Abstract: A user data portion of a flash memory arrangement is grouped into a plurality of mapping units. Each of the mapping units includes a user data memory portion and a metadata portion. The mapping units form a plurality of groups that are associated with at least one lower tier of a forward memory map. For each of the groups, a last written mapping unit within the group is determined. The last written mapping unit includes mapping data in the metadata portion that facilitates determining a physical address of other mapping units within the group. A top tier of the forward memory map is formed that includes at least physical memory locations of the last written mapping units of each of the groups. A physical address of a targeted memory is determined using the top tier and the metadata of the at least one lower tier.

Abstract: Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.

Abstract: The variability of outer code failure rate of memory pages of a solid state memory device can be reduced by selectively grouping the pages included in the outer code words. The data in the page groups are encoded into outer code words which are stored in the memory device. Encoding the data of the page groups and storing the encoded data includes intermittently accumulating an outer code parity as the pages are sequentially stored in the memory device according to a particular order. The pages can be randomly selected for the page groups or can be grouped based on predicted or measured failure rate information. In a memory device having multi-level memory cells, predicting the failure rate of a page can be based on whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page.

Abstract: An apparatus includes a memory that is allocated to reported portions and overprovisioned portions. The apparatus includes an error correction circuit that communicates with the memory in error correction coded data that has a controllable ECC length. The ECC length is a function of a history of error reports. A memory allocation engine balances a size of the overprovisioned portions to maintain a size of the reported portions. The balancing is performed as a function of an average of ECC lengths in the ECC length table over a time interval in which a size of the memory decreases with accumulated erase cycles of the memory.

Abstract: Disc drive data recovery methods and systems that utilize off center track information are provided. A disc drive data track is illustratively read at a first position along a width of the data track and at a second position along the width of the data track. The data read from the track is stored and tagged with indications of the first and the second positions. The tagged data is optionally used to calculate average waveforms for each of the first and the second positions and to identify the average waveform having the highest signal-to-noise ratio.

Abstract: This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.

Abstract: One or more techniques provide majority detection in error recovery. Accordingly, a device retries reading an ECC codeword having one or more bits for a plurality of retries, and stores each retry. The device (“hard” majority detection) votes on a value of each bit of the codeword based on a majority of corresponding retry values in the plurality of corresponding retries. Also, the device (“soft” majority detection) may determine reliability information for a value of each bit of the codeword based on a reoccurrence ratio of corresponding retry values in the plurality of retries. The device may declare erasures based on the reliability information and a (dynamically adjusted) threshold of uncertainty, e.g., where an “uncertain” bit based on the threshold or any symbol with an “uncertain” bit is declared as an erasure.

Abstract: An encoder and method of encoding data words are provided, which map a block of at least one of the data words into an error correction code (ECC) code word. The ECC code word is defined by a plurality of multiple-bit ECC symbols which are separated by boundaries. Bit patterns are constrained from occurring in the ECC code word based on a relative location of the bit patterns to the boundaries.

Abstract: Embodiments of the present invention illustrate various configurations of a channel-to-controller interface. In one embodiment, width of symbols crossing the interface is fixed, as is the clock rate. In other embodiments, the symbol width is variable, and the clock rate is also varied based upon the size of the interface symbol width and the operation of the channel.

Abstract: Methods of encoding and decoding as well as an encoder and decoder are provided for encoding data words into codewords and decoding codewords into data words. The data words are encoded by mapping each data word into a number of data segments. Each data segment is then encoded to form a codeword segment that has the same number of bits as the data word segment. The codeword segments are concatenated to form the codeword. The codewords are decoded by decoding individual codeword segments into data word segments that are the same size as the codeword segments. The data word segments are then mapped into the data word, which has fewer bits than the total number of bits across all data word segments.

Abstract: A detector is provided to detect data values within a data signal that is sampled to provide temporally separated data samples. A first detector portion is configured to determine the location of a first sample vector in a first signal space. A second detector portion is configured to determine the location of a second sample vector in a second signal space. The second detector portion determines the location by using a logic statement to combine a plurality of location indicators. Each location indicator provides the location of the second sample vector relative to a respective boundary surface. The form of the logic statement is independent of the values of the location indicators. In addition, each location indicator is independent of all other location indicators.

Abstract: Embodiments of the present invention illustrate various configurations of a channel-to-controller interface. In one embodiment, width of symbols crossing the interface is fixed, as is the clock rate. In other embodiments, the symbol width is variable, and the clock rate is also varied based upon the size of the interface symbol width and the operation of the channel.