Patents by Inventor Bernd Meyer

Bernd Meyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230412370
    Abstract: Solutions described herein refer to cryptographic data processing, utilizing a first masking scheme of a shared secret and a second masking scheme of the shared secret, wherein a transformation from the first masking scheme to the second masking scheme is conducted by forcing one type of calculation among at least two types of calculations.
    Type: Application
    Filed: June 9, 2023
    Publication date: December 21, 2023
    Inventors: Bernd Meyer, Wieland Fischer
  • Publication number: 20230358793
    Abstract: Embodiments generally relate to a method for allowing power supplied through a cable to be determined. The method comprises receiving magnetic field data, the magnetic field data relating to a magnetic field generated by the cable, receiving reference data, the reference data relating to a current supplied to one or more monitored loads powered through the cable; based on the received magnetic field data and reference data, determining at least one parameter of a function that relates the magnetic field generated by the cable to the power supplied through a cable; and making available the at least one parameter, so that a power supplied by the cable can be determined based on the at least one parameter and a magnetic field value. The one or more monitored loads are a subset of all the loads powered through the cable.
    Type: Application
    Filed: September 22, 2021
    Publication date: November 9, 2023
    Inventors: Bernd MEYER, Joe LOSINNO
  • Publication number: 20220396223
    Abstract: A motor vehicle power cable comprising a flat conductor having an at least rectangular profile, wherein the flat conductor extends along a longitudinal axis, a vertical axis extending along a surface normal of a wide surface of the flat conductor, and a transverse axis extending along a surface normal of a narrow surface of the flat conductor and the flat conductor is bent about the vertical axis and having an inner bend radius and an outer bend radius, characterized in that the flat conductor has at least one forming about the longitudinal axis in the region of the inner bending radius at its inner side edge arranged at the inner bending radius.
    Type: Application
    Filed: August 13, 2020
    Publication date: December 15, 2022
    Inventor: Bernd Meyer
  • Patent number: 11476872
    Abstract: A method is proposed for copying a source array into a target array, wherein both the source array and the target array have at least two elements, wherein each element has a value, in which the elements of the source array are copied into the target array in the sequence of a random permutation, wherein, after a step of copying an element of the source array into the target array, the source array, the target array or the source array and the target array are rotated. A device is also indicated accordingly.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: October 18, 2022
    Assignee: Infineon Technologies AG
    Inventors: Florian Mendel, Bernd Meyer
  • Publication number: 20220232974
    Abstract: A guide device for a moveable furniture part, in particular a drawer, has a catch which is moveable along a guide track and which is pretensioned by an energy store and which is moveable at least between a parked position with a tensioned energy store and an end position with a less tensioned energy store. The energy store can be coupled to an activator between the parked position and the end position in order to transmit a braking or acceleration force to the moveable furniture part, and wherein the activator has a metal support part.
    Type: Application
    Filed: May 4, 2020
    Publication date: July 28, 2022
    Applicant: Paul Hettich GmbH & Co. KG
    Inventors: Bernd MEYER, Britta KLOSS
  • Publication number: 20220188216
    Abstract: A device for processing bit strings of a program flow including a data memory and an interface that is designed to output a second bit string, and a bit string manipulator that is designed to analyze the first bit string at a predetermined bit string section for information that indicates a target state of the program flow, and to manipulate the first bit string in the bit string section to obtain the second bit string.
    Type: Application
    Filed: December 15, 2021
    Publication date: June 16, 2022
    Inventors: Berndt Gammel, Bernd Meyer
  • Patent number: 11342939
    Abstract: It is proposed to divide data read from a memory into groups and to perform a syndrome calculation iteratively based on each of the individual groups. The syndromes may be calculated by means of random access to the individual groups.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: May 24, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Bernd Meyer, Gerd Dirscherl
  • Patent number: 11283469
    Abstract: An integrated circuit for outputting a function value, comprising a pattern matching circuit, configured to compare an input value and multiple transformed versions of the input value with a specified bit pattern, wherein the transformed versions of the input value or the specified bit pattern are created by repeated application of a transformation to the input value or the specified bit pattern, wherein the function is invariant under the transformation or wherein an inverse transformation exists for the transformation, by means of which a change in the function values that is caused by the transformation of the input values can be reversed, a selection circuit configured to select a function value depending on the matching result of the pattern matching circuit and the input value, and an output circuit configured to output a function value for the input value based on the selected function value.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: March 22, 2022
    Assignee: Infineon Technologies AG
    Inventors: Wieland Fischer, Bernd Meyer
  • Publication number: 20220029833
    Abstract: A method for providing challenges to a device comprising (i) compiling a first challenge based on a first random value and a parameter; (ii) compiling a second challenge based on a second random value, the parameter and based on the first challenge or any intermediate result thereof; and (iii) providing the first challenge and the second challenge to the device.
    Type: Application
    Filed: July 21, 2021
    Publication date: January 27, 2022
    Inventors: Thomas Poeppelmann, Wieland Fischer, Bernd Meyer
  • Patent number: 11190337
    Abstract: According to one embodiment, an execution unit is described, which includes a mask generation circuit configured to generate a mask by multiplying a mask generation vector by blocks of codewords of a plurality of cyclic codes, a masking circuit configured to mask data to be processed by means of the mask, and an arithmetic logic unit configured to process the masked data by means of additions and rotations.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: November 30, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Bernd Meyer, Thomas Poeppelmann
  • Patent number: 11086796
    Abstract: A method is provided for accessing a memory via at least one address, wherein the at least one address comprises a codeword of a code. Corresponding devices are also described.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 10, 2021
    Assignee: Infineon Technologies AG
    Inventors: Berndt Gammel, Gerd Dirscherl, Bernd Meyer, Steffen Sonnekalb
  • Publication number: 20210243006
    Abstract: Integrated circuits for modular multiplication of two integers for a cryptographic method, and methods for the cryptographic processing of data based on modular multiplication are herein disclosed. For example, an integrated circuit for modular multiplication of two integers for a cryptographic method has a processor that represents the integers to be multiplied in Montgomery representation with a specified Montgomery representation parameter and a specified modulus, and calculates the result of the modular multiplication of the integers to be multiplied in Montgomery representation iteratively from the least significant word to the most significant word, where for a word calculated in an iteration, the product of the word with a specified factor is added to the words of subsequent iterations, the specified factor given by the product of the negative inverse of the least significant word of the modulus and the modulus, without the least significant word of the product, plus one.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 5, 2021
    Inventor: Bernd MEYER
  • Publication number: 20210159918
    Abstract: An integrated circuit for outputting a function value, comprising a pattern matching circuit, configured to compare an input value and multiple transformed versions of the input value with a specified bit pattern, wherein the transformed versions of the input value or the specified bit pattern are created by repeated application of a transformation to the input value or the specified bit pattern, wherein the function is invariant under the transformation or wherein an inverse transformation exists for the transformation, by means of which a change in the function values that is caused by the transformation of the input values can be reversed, a selection circuit configured to select a function value depending on the matching result of the pattern matching circuit and the input value, and an output circuit configured to output a function value for the input value based on the selected function value.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 27, 2021
    Inventors: Wieland FISCHER, Bernd MEYER
  • Patent number: 10992464
    Abstract: A chip includes a processing device to perform cryptographic operations by secret data; a memory to store a first plurality of information portions that correspond to a first breakdown of the data and from which the secret data are reconstructible by combination of the first plurality of information portions; a random number generator to provide random values; and a conversion device to ascertain second breakdowns of the data into a second plurality of information portions, from which the secret data are reconstructible and to control the memory for an ascertained second breakdown to store the present second plurality of information portions. The conversion device is further configured to ascertain the second breakdowns based on the random values and/or to determine the interval of time between the ascertaining and storing of a second breakdown and the ascertaining and storing of the subsequent second breakdown based on the random values.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: April 27, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Berndt Gammel, Bernd Meyer
  • Patent number: 10992466
    Abstract: One embodiment describes a method for permuting data elements, comprising receiving a sequence of data elements, and carrying out a plurality of interchange operations each comprising randomly selecting a data element from the data elements in the sequence, interchanging the data element with another data element at a deterministically predefined position in the sequence of data elements, and applying a predefined permutation to the deterministically predefined position or to the sequence of data elements.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: April 27, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Wieland Fischer, Bernd Meyer
  • Patent number: 10937469
    Abstract: A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 2, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Jan Otterstedt, Robin Boch, Gerd Dirscherl, Bernd Meyer, Christian Peters, Steffen Sonnekalb
  • Publication number: 20210044306
    Abstract: It is proposed to divide data read from a memory into groups and to perform a syndrome calculation iteratively based on each of the individual groups. The syndromes may be calculated by means of random access to the individual groups.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 11, 2021
    Inventors: Bernd MEYER, Gerd DIRSCHERL
  • Patent number: 10879934
    Abstract: An integrated circuit includes a receiver configured to receive a message word and an integrated hardware decoding circuit. The decoding circuit includes a calculation unit to calculate a syndrome of the message word according to a predetermined BCH code, a logarithmization unit to establish a logarithm of each of one or more syndrome components, an arithmetic circuit to establish a logarithm of each of one or more zeros of the error locator polynomial of the BCH code on the basis of the logarithms of the syndrome components, and a bit inverter circuit to invert the one or more bits of the message word, the positions of which are specified by the logarithms of the zeros of the error locator polynomial. The integrated circuit further includes a data processing circuit to process further the message word processed by the bit inverter circuit.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: December 29, 2020
    Assignee: Infineon Technologies AG
    Inventors: Rainer Goettfert, Bernd Meyer
  • Patent number: 10802059
    Abstract: Described embodiments generally relate to a method of determining power delivered by a cable, the method comprising receiving data related to a residual magnetic field produced by the cable; determining a proportionality factor relating the received data to the power delivered by comparing the residual magnetic field data to independently measured reference data related to the power delivered by the cable; and based on the proportionality factor, determining the power delivered by the cable.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 13, 2020
    Assignee: Dius Computing Pty Ltd
    Inventors: Joe Losinno, Bernd Meyer, Zoran Angelovski, Johny Mattsson
  • Patent number: 10649931
    Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: May 12, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gerd Dirscherl, Benedikt Driessen, Gunther Fenzl, Franz Klug, Bernd Meyer, Steffen Sonnekalb