Abstract: In some examples, a system comprises a capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and the second plates and comprising a Bismuth Metal Oxide-Based Lead Titanate thin film. The capacitor further comprises a dielectric layer disposed on a transistor, wherein the capacitor is disposed on the dielectric layer.

Abstract: An electronic device includes a semiconductor die having a multilevel metallization structure including stacked levels with respective dielectric layers and metal lines, and a low leakage, low hydrogen diffusion barrier layer on one of the stacked levels. The diffusion barrier layer contacts a side of the dielectric layer and the metal line of the one of the stacked levels, and the diffusion barrier layer includes silicon nitride material having a first bond percentage ratio of ammonia to silicon nitride that is greater than a second bond percentage ratio of silicon hydride to silicon nitride.

Abstract: Described examples include a resistor having a substrate having a non-conductive surface and a patterned polysilicon layer on the non-conductive surface, the patterned polysilicon layer including polycrystalline silicon wherein at least 90% of the grains in the polycrystalline silicon are 30 nm or smaller. The resistor also has a first terminal in conductive contact with the patterned polysilicon layer and a second terminal in conductive contact with the polysilicon layer and spaced from the first contact.

Abstract: A system and method for growing fine grain polysilicon. In one example, the method of forming an integrated circuit includes forming a dielectric layer over a semiconductor substrate, and forming a polysilicon layer over the dielectric layer. The polysilicon layer is formed by a chemical vapor deposition process that includes providing a gas flow including disilane and hydrogen gas over the semiconductor substrate.

Abstract: A fin field-effect transistor (“FinFET”) semiconductor device and method of forming the same. In one example, a semiconductor fin is formed over a semiconductor substrate. A conformal dielectric layer is formed on a top and side surfaces of the fin. A doped semiconductor layer is formed over the conformal dielectric layer, the doped semiconductor layer including a dopant. The doped semiconductor layer is heated thereby driving the dopant through the conformal dielectric layer and forming a doped region of the fin.

Abstract: An electronic device includes a first thin film resistor and a second thin film resistor above a dielectric layer that extends in a first plane of orthogonal first and second directions, the first resistor has three portions with the second portion extending between the first and third portions, and a recess etched into the top side of the second portion by a controlled etch process to increase the sheet resistance of the first resistor for dual thin film resistor integration.

Abstract: Apparatus, and their methods of manufacture, that include an insulating feature above a substrate and a resistor formed on the insulating feature. Forming the resistor includes depositing polysilicon and doping the polysilicon (e.g., in-situ) with a carbon dopant and/or an oxygen dopant.

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over the filled trench. A filled via through the second ILD layer provides a connection to the top capacitor plate.

Abstract: In some examples, a method comprises: obtaining a substrate having at a metal interconnect layer deposited over the substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer to the first dielectric layer to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; forming an anti-reflective coating to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form a first metal layer and a second metal layer.

Abstract: Described examples include a resistor having a substrate having a non-conductive surface and a patterned polysilicon layer on the non-conductive surface, the patterned polysilicon layer including polycrystalline silicon wherein at least 90% of the grains in the polycrystalline silicon are 30 nm or smaller. The resistor also has a first terminal in conductive contact with the patterned polysilicon layer and a second terminal in conductive contact with the polysilicon layer and spaced from the first contact.

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

Abstract: In some examples, a system comprises a capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and the second plates and comprising a Bismuth Metal Oxide-Based Lead Titanate thin film. The capacitor further comprises a dielectric layer disposed on a transistor, wherein the capacitor is disposed on the dielectric layer.

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

Abstract: In some examples, a system comprises a capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and the second plates and comprising a Bismuth Metal Oxide-Based Lead Titanate thin film. The capacitor further comprises a dielectric layer disposed on a transistor, wherein the capacitor is disposed on the dielectric layer.

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over the filled trench. A filled via through the second ILD layer provides a connection to the top capacitor plate.

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over including the filled trench. A filled via through the second ILD layer provides a contact to a top plate contact on the top capacitor plate.

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

Abstract: An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over including the filled trench. A filled via through the second ILD layer provides a contact to a top plate contact on the top capacitor plate.

Abstract: In some examples, an integrated circuit includes an isolation layer disposed on or over a semiconductor substrate. The integrated circuit also includes a first conductive plate located over the isolation layer and a composite dielectric layer located over the first conductive plate. The composite dielectric layer includes a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate located directly on the composite dielectric layer above the first conductive plate.

Abstract: In some examples, a method comprises: obtaining a substrate having at a metal interconnect layer deposited over the substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer to the first dielectric layer to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; forming an anti-reflective coating to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form a first metal layer and a second metal layer.