Abstract: An electrically programmable memory cell is of the type having a floating gate and a control gate laterally spaced apart, and both insulated from a substrate. The floating gate and the control gate are made by a self-aligned method wherein, a first layer of silicon dioxide is provided on the substrate. A first layer of polysilicon is then provided on the first layer of silicon dioxide. The first layer of polysilicon is patterned and selective portions are removed. A second layer of silicon dioxide is provided on the patterned first layer of polysilicon. Portions of the second layer of silicon dioxide are selectively masked to define regions in the corresponding first layer of polysilicon which would become the floating gate. The second layer of silicon dioxide is anisotropically etched. The second layer of silicon dioxide is then isotropically etched. The first layer of polysilicon is anisotropically etched to defined the floating gate.

Abstract: An electrically programmable memory cell is of the type having a floating gate and a control gate laterally spaced apart, and both insulated from a substrate. The floating gate and the control gate are made by a self-aligned method wherein, a first layer of silicon dioxide is provided on the substrate. A first layer of polysilicon is then provided on the first layer of silicon dioxide. The first layer of polysilicon is patterned and selective portions are removed. A second layer of silicon dioxide is provided on the patterned first layer of polysilicon. Portions of the second layer of silicon dioxide are selectively masked to define regions in the corresponding first layer of polysilicon which would become the floating gate. The second layer of silicon dioxide is anisotropically etched. The second layer of silicon dioxide is then isotropically etched. The first layer of polysilicon is anisotropically etched to defined the floating gate.

Abstract: An electrically programmable memory cell is of the type having a floating gate and a control gate laterally spaced apart, and both insulated from a substrate. The floating gate and the control gate are made by a self-aligned method wherein, a first layer of silicon dioxide is provided on the substrate. A first layer of polysilicon is then provided on the first layer of silicon dioxide. The first layer of polysilicon is patterned and selective portions are removed. A second layer of silicon dioxide is provided on the patterned first layer of polysilicon. Portions of the second layer of silicon dioxide are selectively masked to define regions in the corresponding first layer of polysilicon which would become the floating gate. The second layer of silicon dioxide is anisotropically etched. The second layer of silicon dioxide is then isotropically etched. The first layer of polysilicon is anisotropically etched to defined the floating gate.

Abstract: A single transistor electrically programmable and erasable memory cell is disclosed. The single transistor has a source, a drain with a channel region therebetween, defined on a substrate. A first insulating layer is over the source, channel and drain regions. A floating gate is positioned on top of the first insulating layer over a portion of the channel region and over a portion of the source region. A second insulating layer has a top wall which is over the floating gate, and a side wall which is adjacent thereto. A control gate has a first portion which is over the first insulating layer and immediately adjacent to the side wall of the second insulating layer. The control gate has a second portion which is over the top wall of the second insulating layer and is over the floating gate. Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate.

Abstract: A self-aligned ion-implantation method for making a split-gate single transistor non-volatile electrically alterable semiconductor memory cell is disclosed. The method uses a silicon substrate. A layer of dielectric material is grown over the substrate. A layer of silicon is grown over the dielectric material. The silicon is masked to define a floating gate region. Ions then are implanted in the layer of silicon in the floating gate region to render the region conductive. Ions are then implanted through the floating gate region into the substrate to define the threshold in the substrate beneath the floating gate region. The floating gate region is then oxidized and patterned to form the floating gate. A second layer of dielectric material is deposited over the floating gate and over the substrate. A control gate is patterned and formed. The drain and the source regions in the substrate are defined.

Abstract: A methd of making an electrically programmable and erasable memory device having a re-crystallized floating gate is disclosed. A substrate is first defined. A first layer of dielectric material is grown over the substrate. A layer of polysilicon or amorphous silicon is then deposited over the first layer. The layer of silicon is covered with a protective material and is annealed to form recrystallized silicon. A portion of the protective material is removed to define a floating gate region. Making oxide is grown on the floating gate region. The remainder of the protective material and the recrystallized silicon thereunder is removed. A second layer of dielectric material is formed over the floating gate and over the substrate, immediately adjacent to the floating gate. A control gate is patterned and formed. Source and drain regions are then defined in the substrate.

Abstract: A single transistor electrically programmable and erasable memory cell is disclosed. The single transistor has a source, a drain with a channel region therebetween, defined on a substrate. A first insulating layer is over the source, channel and drain regions. A floating gate is positioned on top of the first insulating layer over a portion of the channel region and over a portion of the drain region. A second insulating layer has a top wall which is over the floating gate, and a side wall which is adjacent thereto. A control gate has a first portion which is over the first insulating layer and immediately adjacent to the side wall of the second insulating layer. The control gate has a second portion which is over the top wall of the second insulating layer and is over the floating gate. Erasure of the cell is accomplished by the mechanism of Fowler-Nordheim tunneling from the floating gate through the second insulating layer to the control gate.

Abstract: A nonvolatile integrated circuit memory cell (10) is provided which is smaller in size than conventional memory cells and uses only two layers of polysilicon with floating gate portion (50) of the memory cell formed partly from a first polysilicon layer (20) and partly from second polysilicon layer (26), contact between the two portions being made using residual polysilicon bridge or overlapping portion (34) between the two layers. The invention enables programming and erase tunneling oxides to be formed in a single step while maximizing the capacitive coupling between the floating gate (50) and the substrate (12) by forming a silicon dioxide layer (102) between the floating gate and substrate separately from formation of the programming (30) and erase (28) tunneling elements.