Abstract: Integrated circuit structures having metal gates with tapered plugs, and methods of fabricating integrated circuit structures having metal gates with tapered plugs, are described. For example, includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin. The dielectric gate plug is on the STI structure, and the dielectric gate plug has sides tapered outwardly from a top of the dielectric gate plug to a bottom of the dielectric gate plug.

Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.

Abstract: Gate-all-around integrated circuit structures having nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of horizontal nanowires; and a doped nucleation layer at a base of the epitaxial source or drain structures adjacent to the sub-fin. Where the integrated circuit structure comprises an NMOS transistor, doped nucleation layer comprises a carbon-doped nucleation layer. Where the integrated circuit structure comprises a PMOS transistor, doped nucleation layer comprises a heavy boron-doped nucleation layer.

Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

Abstract: Dummy gate patterning lines, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a first gate line along a first direction. A second gate line is parallel with the first gate line along the first direction. A third gate line extends between and is continuous with the first gate line and the second gate line along a second direction, the second direction orthogonal to the first direction.

Abstract: Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.

Abstract: Embodiments disclosed herein include semiconductor devices and methods of making semiconductor devices. In an embodiment, a semiconductor device comprises a substrate, where the substrate is a dielectric material, and a vertical stack of semiconductor channels over the substrate. In an embodiment, the semiconductor device further comprises a source at a first end of the semiconductor channels, a drain at a second end of the semiconductor channels, and a barrier between a bottom surface of the source and the substrate.

Abstract: Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Abstract: Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

Abstract: Integrated circuit structures having plugged metal gates, and methods of fabricating integrated circuit structures having plugged metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on the STI structure. The gate dielectric material layer and the conductive gate layer are along a side of the dielectric gate plug, and the gate dielectric material layer is in direct contact with an entirety of the side of the dielectric gate plug.

Abstract: Fin cuts in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a horizontal stack of semiconductor nanowire portions. A dielectric gate spacer is vertically over the horizontal stack of semiconductor nanowire portions. A gate isolation structure is laterally adjacent to a first side of the horizontal stack of semiconductor nanowire portions. A source or drain isolation structure is laterally adjacent to a second side of the horizontal stack of semiconductor nanowire portions.

Abstract: Integrated circuit structures having metal gates with reduced aspect ratio cuts, and methods of fabricating integrated circuit structures having metal gates with reduced aspect ratio cuts, are described. For example, an integrated circuit structure includes a sub-fin having a portion protruding above a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric structure is laterally spaced apart from the plurality of horizontally stacked nanowires. A dielectric gate plug is landed on the dielectric structure.

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

Abstract: Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

Abstract: Gate aligned fin cut for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment. A first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment. A second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment. An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

Abstract: Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.

Abstract: Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.