Abstract: An apparatus and a method for optimizing data streaming in a computer system utilizing random access memory in a system logic device have been presented. In one embodiment, the apparatus includes a processor interface unit and a cache to store information received from a processor coupled to the processor interface unit, the cache to store disposable information that may be overwritten without ever having delivered the disposable information to a system memory if the disposable information has been read at least once, the processor interface unit to receive a disposable information attribute indication from the processor when the processor delivers the disposable information to the processor interface unit.

Abstract: A method and apparatus for a dedicated cache memory are described. Under an embodiment of the invention, a cache memory includes a general-purpose sector and a dedicated sector. The general-purpose sector is to be used for general computer operations. The dedicated sector is to be dedicated to use for a first computer process.

Abstract: One embodiment of an apparatus for optimizing data streaming in a computer system between a processor and a system component includes a cache in a system logic device that stores disposable information. The term “disposable information” is defined as information that is meant to be read by a system component only once. Once a particular cache entry containing disposable information is read by a system component, that cache entry may be overwritten. Because disposable information is meant to be read only once, there is no need for the cache to write the information to system memory before overwriting the cache entry.

Abstract: An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected to at least one processor to control a memory in response to instructions from the at least one processor. An I/O controller is connected to the memory controller to control data flow to at least one device in response to instructions from the at least one processor. Lock down logic stores captured cycle information on a processor cycle that results in interrupt.

Abstract: A method, apparatus, system, and machine-readable medium to bound data transmission latency by transmitting error verification data at a point during a data transmission based upon loading of a channel for the data transmission is provided. Embodiments may comprise determining the loading of a communication channel and transmitting error verification data to a target device based upon the loading. More specifically, some embodiments transmit error verification data at intervals, variable intervals in some embodiments, to balance transmission latency against the bandwidth available from a communication medium.

Abstract: A bus architecture arrangement is provided. Embodiments provide for a point-to-point protocol of a bused system, such as a processor-based system. Further embodiments may comprise a dynamically configurable point-to-point communication array with connectors and/or translators to couple hub devices with endpoint devices. Some of the connectors and/or translators may inductively or magnetically couple endpoint devices to and decouple endpoint devices from point-to-point communication media to facilitate efficient use of a point-to-point communication array.

Abstract: The present invention is a method and apparatus to control cache. A processor cache unit processes a cache access request from a processor core of a processor. The processor cache unit includes a processor cache controller and a processor cache. A chipset cache controller controls a chipset cache located in a chipset in response to the cache access request from the processor core. The chipset is coupled to the processor via a bus.

Abstract: A method, apparatus, system, and machine-readable medium to bound data transmission latency by transmitting error verification data at a point during a data transmission related to a data transmission event is provided. Embodiments may comprise receiving an indication of a data transmission event, such as an end of a packet, and transmitting error verification data to a target device based upon the indication. More specifically, some embodiments transmit error verification data at an end of a packet to balance transmission latency against the bandwidth available from a communication medium.

Abstract: A RDRAM memory controller is provided to couple to a channel that is further coupled to a first RDRAM device and a second RDRAM device. The memory controller may include a command queue to store a plurality of commands and scheduling logic to schedule the plurality of commands to shift from the command queue based on a clock signal. Delaying logic may be provided to delay at least one command after the command shifts from the command queue. The delaying logic may include a plurality of multiplexors and a delay register coupled to outputs of the command queue.

Abstract: A circuit comprising a first register and a second register to store the first and second status of the plurality of memory banks. Also, the circuit comprises a logic and an encoder circuit. The logic is coupled to the first and second registers and generates a third status of the plurality of memory banks based on the first and second status. The encoder coupled to the logic generates a refresh request in response to the third status of the plurality of memory banks.

Abstract: A method for a cache line replacement policy enhancement to avoid memory page thrashing. The method of one embodiment comprises comparing a memory request address with cache tags to determine if any cache entry in set ‘n’ can match the address. The address is masked to determine if a thrash condition exists. Allocation to set ‘n’ is discouraged if a thrash condition is present.

Abstract: In one embodiment, monitoring data traffic through a memory controller; and dynamically and automatically selecting a burst length for data transactions through a memory controller in response to the monitored data traffic.

Abstract: A method and apparatus of dynamically adjusting a memory system's existing paging policy is disclosed. In one embodiment, the method for dynamically adjusting the paging policy generates a select signal according to at least one input signal and the existing paging policy to the memory system and proceeds to modify the existing paging policy basing on the generated select signal.

Abstract: A bus architecture arrangement is provided. Embodiments provide for a point-to-point protocol of a bused system, such as a processor-based system. Further embodiments may comprise a dynamically configurable point-to-point communication array with connectors and/or translators to couple hub devices with endpoint devices. Some of the connectors and/or translators may inductively or magnetically couple endpoint devices to and decouple endpoint devices from point-to-point communication media to facilitate efficient use of a point-to-point communication array.

Abstract: A method for a cache line replacement policy enhancement to avoid memory page thrashing. The method of one embodiment comprises comparing a memory request address with cache tags to determine if any cache entry in set ‘n’ can match the address. The address is masked to determine if a thrash condition exists. Allocation to set ‘n’ is discouraged if a thrash condition is present.

Abstract: A method, apparatus, system, and machine-readable medium to bound data transmission latency by transmitting error verification data at a point during a data transmission based upon loading of a channel for the data transmission is provided. Embodiments may comprise determining the loading of a communication channel and transmitting error verification data to a target device based upon the loading. More specifically, some embodiments transmit error verification data at intervals, variable intervals in some embodiments, to balance transmission latency against the bandwidth available from a communication medium.

Abstract: A method, apparatus, system, and machine-readable medium to bound data transmission latency by transmitting error verification data at a point during a data transmission related to a data transmission event is provided. Embodiments may comprise receiving an indication of a data transmission event, such as an end of a packet, and transmitting error verification data to a target device based upon the indication. More specifically, some embodiments transmit error verification data at an end of a packet to balance transmission latency against the bandwidth available from a communication medium.

Abstract: A method for a cache line replacement policy enhancement to avoid memory page thrashing. The method of one embodiment comprises comparing a memory request address with cache tags to determine if any cache entry in set ‘n’ can match the address. The address is masked to determine if a thrash condition exists. Allocation to set ‘n’ is discouraged if a thrash condition is present.

Abstract: A RDRAM memory controller is provided to couple to a channel that is further coupled to a first RDRAM device and a second RDRAM device. The memory controller may include a command queue to store a plurality of commands and scheduling logic to schedule the plurality of commands to shift from the command queue based on a clock signal. Delaying logic may be provided to delay at least one command after the command shifts from the command queue. The delaying logic may include a plurality of multiplexors and a delay register coupled to outputs of the command queue.

Abstract: A method and apparatus of enforcing a connection policy of a system controller is disclosed. In one embodiment, the method and apparatus monitor multiple distinct device identifications on a bus connected to the system controller. When more than a threshold number of the device identifications have been identified on the bus, the method and apparatus proceed to disable the system controller.