Abstract: A method and apparatus to reduce processor bus loading is provided. A method of reducing processor bus loading in a system having a processor with a first processor bus granularity, a memory controller, and an ownership tracker. First, a set of data is requested from a memory controller, the set of data being smaller than the processor bus granularity. If the memory controller does not own the set of data, performing a processor bus snoop to determine if a processor cache owns the set of data. If the processor cache owns the set of data, assigning ownership of a block of data having a size equal to the processor bus granularity to the memory controller. The memory controller returning the set of data requested by an I/O agent to the I/O agent.

Abstract: The present invention is a method and apparatus to control cache. A processor cache unit processes a cache access request from a processor core of a processor. The processor cache unit includes a processor cache controller and a processor cache. A chipset cache controller controls a chipset cache located in a chipset in response to the cache access request from the processor core. The chipset is coupled to the processor via a bus.

Abstract: The present invention is a method and apparatus to monitor prefetch requests. A storage circuit is coupled to a prefetcher to store a plurality of prefetch addresses which corresponds to most recent prefetch requests from a processor. The prefetcher generates an access request to a memory when requested by the processor. A canceler cancels the access request when the access request corresponds to at least P of the stored prefetch addresses. P is a non-zero integer.

Abstract: An information capturing technique captures information on a processor cycle that results in a high level interrupt, such as an SMI (System Management Interrupt). A memory controller is connected to at least one processor to control a memory in response to instructions from the at least one processor. An I/O controller is connected to the memory controller to control data flow to at least one device in response to instructions from the at least one processor. Lock down logic stores captured cycle information on a processor cycle that results in interrupt.

Abstract: One embodiment of an apparatus for optimizing data streaming in a computer system between a processor and a system component includes a cache in a system logic device that stores disposable information. The term “disposable information” is defined as information that is meant to be read by a system component only once. Once a particular cache entry containing disposable information is read by a system component, that cache entry may be overwritten. Because disposable information is meant to be read only once, there is no need for the cache to write the information to system memory before overwriting the cache entry.

Abstract: A method and system for storing a set of data representing a memory configuration in a first memory. The set of data represents a first memory configuration of a second memory. The set of data is transmitted from the first memory to the second memory if the first memory configuration has changed.

Abstract: The present invention provides a method, apparatus, and system for dynamically changing the sizes of power-control pools that are used to control the power consumption levels of memory devices. In one embodiment, a request to change the sizes of the memory power-control pools is received. In response to receiving the request to change the sizes of the memory power-control pools, the memory devices are placed in a specific operating mode or power state after being refreshed in a periodic refresh cycle. In response to a signal indicating that all memory devices have been placed in the specific operating mode, powercontrol pools are resized according to pool size values corresponding to the request received.