Abstract: Provided is an M2-LVP-K1 virus including a colorectal cancer cell-specific mutant sialic acid binding domain and a composition for treating colorectal cancer including the same. The mutant sialic acid binding domain is constructed using directed evolution technology, and is a recombinant Newcastle disease virus constructed by substituting a normal sialic acid binding domain for a HN protein, a cell-binding receptor, to improve the specific infectivity to HCT116 cells. It was identified that M2-LVP-K1 recombinant Newcastle disease virus with improved colorectal cancer cell-specific infectivity has improved HCT116 cell death effect compared to the conventional normal recombinant Newcastle disease virus, and produces an excellent effect in inhibiting cancer tissue growth through in vivo experiments.

Abstract: The present disclosure relates to an M2-LVP-K1 virus including a colorectal cancer cell-specific mutant sialic acid binding domain and a composition for treating colorectal cancer including the same. The mutant sialic acid binding domain of the present disclosure is constructed using directed evolution technology, and is a recombinant Newcastle disease virus constructed by substituting a normal sialic acid binding domain for a HN protein, a cell-binding receptor, to improve the specific infectivity to HCT116 cells. It was identified that M2-LVP-K1 recombinant Newcastle disease virus with improved colorectal cancer cell-specific infectivity has improved HCT116 cell death effect compared to the conventional normal recombinant Newcastle disease virus, and produces an excellent effect in inhibiting cancer tissue growth through in vivo experiments.

Abstract: Provided are an oncolytic virus for treating brain tumors using a recombinant Newcastle disease virus into which a Newcastle disease virus (NDV) vector-based PTEN (phosphatase and tensin homolog) gene is inserted and a composition for treating brain tumors using the same which can be used for a therapeutic viral agent that can induce reduction of clinical symptoms or partial or complete remission through brain tumor cell death or brain tumor tissue reduction by expressing normal PTEN protein after being infected with brain tumor cells, as a recombinant Newcastle disease virus containing a human PTEN protein gene.

Abstract: Provided are an oncolytic virus for treating brain tumors using a recombinant Newcastle disease virus into which a Newcastle disease virus (NDV) vector-based PTEN (phosphatase and tensin homolog) gene is inserted and a composition for treating brain tumors using the same which can be used for a therapeutic viral agent that can induce reduction of clinical symptoms or partial or complete remission through brain tumor cell death or brain tumor tissue reduction by expressing normal PTEN protein after being infected with brain tumor cells, as a recombinant Newcastle disease virus containing a human PTEN protein gene.

Abstract: The present disclosure relates to a vaccine composition for preventing human infection SARS-CoV-2 (COVID-19) and alleviating infection symptoms, and the vaccine composition including a recombinant Newcastle disease virus on the surface of which the SARS-CoV-2 RBD protein of the present disclosure is expressed or antigen purified therefrom induces an immune response that can fight COVID-19 infection so that it can be useful as a vaccine for preventing and treating SARS-CoV-2 infection.

Abstract: According to one embodiment, an insulating layer is formed on a substrate. A hole is formed in the insulating layer. A metal layer is formed in the hole to fill the hole. A surface of the insulating layer and a surface of the metal layer is removed by etching with ion beams having a first angle, which etches both the insulating layer and the metal layer at a first etching rate. A resistance change element is formed on the metal layer.

Abstract: According to one embodiment, an insulating layer is formed on a substrate. A hole is formed in the insulating layer. A metal layer is formed in the hole to fill the hole. A surface of the insulating layer and a surface of the metal layer is removed by etching with ion beams having a first angle, which etches both the insulating layer and the metal layer at a first etching rate. A resistance change element is formed on the metal layer.

Abstract: A method for fabricating an electronic device including a semiconductor memory includes: forming a variable resistance element including material layers over a substrate; forming a hard mask layer including a metal over the material layers; selectively etching the hard mask layer to form an etched hard mask layer; etching the material layers by using the etched hard mask layer as an etch barrier, the etching of the material layers providing an etch byproduct formed on sidewalls of the etched material layers and the etch byproduct including a material that is more readily oxidized than the metal of the hard mask layer; and performing a treatment using a gas or plasma to suppresses oxidation of the hard mask layer and facilitate oxidation of the etch byproducts.

Abstract: In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas.

Abstract: A TFT array substrate is provided. The TFT array substrate includes a gate electrode connected to a gate line; a source electrode connected to a data line, the data line crossing the gate line to define a pixel region; a drain electrode facing the source electrode with a channel interposed therebetween; a semiconductor layer forming the channel between the source electrode and the drain electrode; a channel passivation layer formed on the channel to protect the semiconductor layer; a pixel electrode disposed in the pixel region to contact with the drain electrode; a storage capacitor including the pixel electrode extending over the gate line to form a storage area on a gate insulating layer on which a semiconductor layer pattern and a metal layer pattern are stacked; a gate pad extending from the gate line; and a data pad connected to the data line.

Abstract: A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line.

Abstract: In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas.

Abstract: In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas.

Abstract: A method for manufacturing a semiconductor memory device includes sequentially depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, a first top electrode layer, a second top electrode layer and a mask layer, etching the mask layer and forming a mask pattern, etching the second top electrode layer and the first top electrode layer by using the mask pattern as an etch barrier, etching the MTJ layer by using the mask layer and the second top electrode layer as an etch barrier, and etching the bottom electrode layer by using the first top electrode layer as an etch barrier.

Abstract: A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad.

Abstract: A method for fabricating a semiconductor device includes forming a bottom-electrode metal layer over a substrate, planarizing the bottom-electrode metal layer by a first thickness through a chemical mechanical polishing (CMP) process, etching the bottom-electrode metal layer by a second thickness through a wet etching process, forming a plurality of layers of a magnetic tunneling junction (MTJ) element over the bottom-electrode metal layer, forming a top electrode over the plurality of layers, and forming the MTJ element and a bottom electrode by etching the plurality of layers and the bottom-electrode metal layer using the top electrode as an etch mask.

Abstract: A method for manufacturing a semiconductor memory device includes sequentially depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, a first top electrode layer, a second top electrode layer and a mask layer, etching the mask layer and forming a mask pattern, etching the second top electrode layer and the first top electrode layer by using the mask pattern as an etch barrier, etching the MTJ layer by using the mask layer and the second top electrode layer as an etch barrier, and etching the bottom electrode layer by using the first top electrode layer as an etch barrier.

Abstract: Provided is an array substrate for an IPS-mode LCD device and method of fabricating the same that prevents a problem referred to as wavy noise. The IPS-mode LCD device and method have a shorter processing time and low error rate without an increase in fabrication and production costs.

Abstract: In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas.

Abstract: A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate line, a gate pad, a gate electrode, and a data pad on a substrate through a first mask process, forming a gate insulating layer on a substantial part of an entire surface of the substrate including the gate line, the gate pad, the gate electrode, and the data pad, forming a data line, a source-drain pattern and an active layer on the gate insulating layer and forming a gate pad contact hole and a data pad contact hole in the gate insulating layer through a second mask process, and forming a pixel electrode, a gate pad terminal, a data pad terminal, a source electrode, a drain electrode, and an ohmic contact layer through a third mask process.