Patents by Inventor Bo-Kyoung Jung

Bo-Kyoung Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120018826
    Abstract: A method for manufacturing a semiconductor memory device includes sequentially depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, a first top electrode layer, a second top electrode layer and a mask layer, etching the mask layer and forming a mask pattern, etching the second top electrode layer and the first top electrode layer by using the mask pattern as an etch barrier, etching the MTJ layer by using the mask layer and the second top electrode layer as an etch barrier, and etching the bottom electrode layer by using the first top electrode layer as an etch barrier.
    Type: Application
    Filed: July 21, 2011
    Publication date: January 26, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventors: Min Suk LEE, Byung Gu Gyun, Bo Kyoung Jung, Chang Hyup Shin
  • Publication number: 20100323482
    Abstract: A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line.
    Type: Application
    Filed: August 27, 2010
    Publication date: December 23, 2010
    Inventors: Young Seok CHOI, Hong Woo Yu, Ki Sul Cho, Jae Ow Lee, Bo Kyoung Jung
  • Publication number: 20100315584
    Abstract: Provided is an array substrate for an IPS-mode LCD device and method of fabricating the same that prevents a problem referred to as wavy noise. The IPS-mode LCD device and method have a shorter processing time and low error rate without an increase in fabrication and production costs.
    Type: Application
    Filed: August 4, 2010
    Publication date: December 16, 2010
    Inventors: Ki-Sul Cho, Young-Seok Choi, Byung-Yong Ahn, Tae-Ung Hwang, Dong-Jun Min, Bo-Kyoung Jung
  • Patent number: 7804089
    Abstract: A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: September 28, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Young Seok Choi, Hong Woo Yu, Ki Sul Cho, Jae Ow Lee, Bo Kyoung Jung
  • Patent number: 7796225
    Abstract: Provided is an array substrate for an IPS-mode LCD device and method of fabricating the same that prevents a problem referred to as wavy noise. The IPS-mode LCD device and method have a shorter processing time and low error rate without an increase in fabrication and production costs.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: September 14, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Ki-Sul Cho, Young-Seok Choi, Byung-Yong Ahn, Tae-Ung Hwang, Dong-Jun Min, Bo-Kyoung Jung
  • Publication number: 20100075472
    Abstract: A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad.
    Type: Application
    Filed: November 25, 2009
    Publication date: March 25, 2010
    Inventors: Young Seok Choi, Hong Woo Yu, Ki Sul Cho, Jae Ow Lee, Bo Kyoung Jung
  • Patent number: 7646018
    Abstract: A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: January 12, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Young Seok Choi, Hong Woo Yu, Ki Sul Cho, Jae Ow Lee, Bo Kyoung Jung
  • Patent number: 7589030
    Abstract: A method of fabricating a liquid crystal display device includes performing a first mask process to form a gate line, a gate pad, and a gate electrode on a substrate. The method of fabricating a liquid crystal display device further includes performing a second mask process to form an active layer on the gate electrode, performing a third mask process to form a pixel electrode contacting the active layer, and performing a fourth mask process to form a source electrode and a drain electrode on the active layer.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: September 15, 2009
    Assignee: LG. Display Co., Ltd.
    Inventors: Ki Sul Cho, Young Seok Choi, Byung Yong Ahn, Tae Ung Hwang, Dong Jun Min, Bo Kyoung Jung
  • Publication number: 20090159895
    Abstract: A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate line, a gate pad, a gate electrode, and a data pad on a substrate through a first mask process, forming a gate insulating layer on a substantial part of an entire surface of the substrate including the gate line, the gate pad, the gate electrode, and the data pad, forming a data line, a source-drain pattern and an active layer on the gate insulating layer and forming a gate pad contact hole and a data pad contact hole in the gate insulating layer through a second mask process, and forming a pixel electrode, a gate pad terminal, a data pad terminal, a source electrode, a drain electrode, and an ohmic contact layer through a third mask process.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 25, 2009
    Inventors: Ki-Sul Cho, Young-Seok Choi, Byung-Yong Ahn, Tae-Ung Hwang, Dong-Jun Min, Bo-Kyoung Jung
  • Patent number: 7479419
    Abstract: A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate line, a gate pad, a gate electrode, and a data pad on a substrate through a first mask process, forming a gate insulating layer on a substantial part of an entire surface of the substrate including the gate line, the gate pad, the gate electrode, and the data pad, forming a data line, a source-drain pattern and an active layer on the gate insulating layer and forming a gate pad contact hole and a data pad contact hole in the gate insulating layer through a second mask process, and forming a pixel electrode, a gate pad terminal, a data pad terminal, a source electrode, a drain electrode, and an ohmic contact layer through a third mask process.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: January 20, 2009
    Assignee: LG Display Co., Ltd.
    Inventors: Ki-Sul Cho, Young-Seok Choi, Byung-Yong Ahn, Tae-Ung Hwang, Dong-Jun Min, Bo-Kyoung Jung
  • Publication number: 20070153198
    Abstract: Provided is an array substrate for an IPS-mode LCD device and method of fabricating the same that prevents a problem referred to as wavy noise. The IPS-mode LCD device and method have a shorter processing time and low error rate without an increase in fabrication and production costs.
    Type: Application
    Filed: December 15, 2006
    Publication date: July 5, 2007
    Inventors: Ki-sul Cho, Young-Seok Choi, Byung-Yong Ahn, Tae-Ung Hwang, Dong-Jun Min, Bo-Kyoung Jung
  • Publication number: 20060262244
    Abstract: A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate line, a gate pad, a gate electrode, and a data pad on a substrate through a first mask process, forming a gate insulating layer on a substantial part of an entire surface of the substrate including the gate line, the gate pad, the gate electrode, and the data pad, forming a data line, a source-drain pattern and an active layer on the gate insulating layer and forming a gate pad contact hole and a data pad contact hole in the gate insulating layer through a second mask process, and forming a pixel electrode, a gate pad terminal, a data pad terminal, a source electrode, a drain electrode, and an ohmic contact layer through a third mask process.
    Type: Application
    Filed: December 16, 2005
    Publication date: November 23, 2006
    Inventors: Ki-Sul Cho, Young-Seok Choi, Byung-Yong Ahn, Tae-Ung Hwang, Dong-Jun Min, Bo-Kyoung Jung