Patents by Inventor Bo Yu

Bo Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113202
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
  • Publication number: 20240113201
    Abstract: Methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. Thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. In some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially V-shaped recesses. In some embodiments, the method further includes forming a substantially V-shaped inner spacer within the substantially V-shaped recesses.
    Type: Application
    Filed: January 25, 2023
    Publication date: April 4, 2024
    Inventors: Chih-Ching WANG, Wei-Yang LEE, Bo-Yu LAI, Chung-I YANG, Sung-En LIN
  • Publication number: 20240114207
    Abstract: A media docking device includes an input module, an output module and a processing module. The input module is electrically connected to a media source device for receiving media data. The output module is electrically connected to a media play device. The processing module determines if an instruction is received from the media source device or a remote device. If the instruction is not received, the processing module transfers the media data to the output module to transmit to the media play device. If the instruction is received, the processing module limits a transmission of the media data according to the instruction, such that the media data will not be completely played by the media play device.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 4, 2024
    Inventors: Chien-Wei CHEN, Tsung-Han LI, You-Wen CHIOU, Kuan-Chi CHOU, Bo Yu LAI
  • Publication number: 20240111849
    Abstract: A media docking device includes an input circuit, an output circuit and a processing circuit. The input circuit is electrically connected to a media source device for receiving media data. The output circuit is electrically connected to a media play device. The processing circuit is electrically connected to the input circuit and the output circuit. The processing circuit determines if a verification procedure is passed. If the verification procedure is passed, the processing circuit transfers the media data to the media play device. If the verification procedure is not passed, the processing circuit limits a transmission of the media data, such that the media data will not be completely played by the media play device.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 4, 2024
    Inventors: Chien-Wei CHEN, Tsung-Han LI, You-Wen CHIOU, Kuan-Chi CHOU, Bo Yu LAI
  • Publication number: 20240103097
    Abstract: The present disclosure provides a direct current (DC) transformer error detection apparatus for a pulsating harmonic signal, including a DC and pulsating harmonic current output module and an external detected input module, where the DC and pulsating harmonic current output module outputs a DC and a DC superimposed pulsating harmonic current to an internal sampling circuit and a self-calibrated standard resistor array; and the internal sampling circuit converts the input DC and the input DC superimposed pulsating harmonic current into a voltage signal, and sends the voltage signal to an analog-to-digital (AD) sampling and measurement component through a front-end conditioning circuit and a detected input channel. The DC transformer error detection apparatus can complete self-calibration for measurement of the DC and the pulsating harmonic signal on a test site.
    Type: Application
    Filed: August 17, 2022
    Publication date: March 28, 2024
    Inventors: Xin Zheng, Wenjing Yu, Tao Peng, Yi Fang, Ming Lei, Hong Shi, Ben Ma, Li Ding, Wei Wei, Linghua Li, He Yu, Tian Xia, Yingchun Wang, Sike Wang, Dongri Xie, Xin Wang, Bo Pang, Xianjin Rong
  • Publication number: 20240100488
    Abstract: Provided are a high temperature-resistant composite nanofiltration membrane and a preparation method thereof. The high temperature-resistant composite nanofiltration membrane includes a base membrane and a polyamide membrane arranged on the base membrane; wherein the polyamide membrane is prepared from raw materials comprising: an amine, an inorganic salt, a silane additive, a polyacyl chloride, and an oil phase solvent; and the silane additive is at least one selected from the group consisting of 3-aminopropyltriethoxysilane, divinyltriaminopropyltrimethoxysilane, N-cyclohexyl-?-aminopropyltrimethoxysilane, and trimethoxy[3-(phenylamino)propyl]silane.
    Type: Application
    Filed: July 13, 2023
    Publication date: March 28, 2024
    Inventors: Hui YU, Hongwei LU, Bo PENG, Qunhui HU, Qian LIAO, Pan HE, Yanbo HE, Jun PENG
  • Patent number: 11942448
    Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bo-Hsun Pan, Hung-Yu Chou, Chung-Hao Lin, Yuh-Harng Chien
  • Patent number: 11943340
    Abstract: In some examples, for process-to-process communication, such as in function linking, a virtual channel can be provisioned to provide virtual machine to virtual machine communications. In response to a transmit request from a source virtual machine, the virtual channel can cause a data copy from a source buffer associated with the source virtual machine without decryption or encryption. The virtual channel provisions a key identifier for the copied data. The destination virtual machine can receive an indication data is available and can cause the data to be decrypted using a key accessed using the key identifier and source address of the copied data. In addition, the data can be encrypted using a second, different key for storage in a destination buffer associated with the destination virtual machine. In some examples, the key identifier and source address is managed by the virtual channel and is not visible to virtual machine or hypervisor.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Bo Cui, Cunming Liang, Jr-Shian Tsai, Ping Yu, Xiaobing Qian, Xuekun Hu, Lin Luo, Shravan Nagraj, Xiaowen Zhang, Mesut A. Ergin, Tsung-Yuan C. Tai, Andrew J. Herdrich
  • Patent number: 11941821
    Abstract: An image sleep analysis method and system thereof are disclosed. During sleep duration, a plurality of visible-light images of a body are obtained. Positions of image differences are determined by comparing the visible-light images. A plurality of features of the visible-light images are identified and positions of the features are determined. According to the positions of the image differences and features, the motion intensities of the features are determined. Therefore, a variation of the motion intensities is analyzed and recorded to provide accurate sleep quality.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: March 26, 2024
    Assignee: YUN YUN AI BABY CAMERA CO., LTD.
    Inventors: Bo-Zong Wu, Meng-Ta Chiang, Chia-Yu Chen, Shih-Yun Shen
  • Publication number: 20240098753
    Abstract: A method comprises: a second communication apparatus sends a trigger frame, to trigger at least one first communication apparatus that includes a first communication apparatus to transmit an uplink PPDU. After receiving the trigger frame, the at least one first communication apparatus sends the PPDU to the second communication apparatus based on the trigger frame. The PPDU includes a data field and an STF sequence, the data field is carried in a distributed RU, the distributed RU includes a plurality of subcarrier groups that are discrete in frequency domain, one of the subcarrier groups includes one subcarrier or includes at least two consecutive subcarriers, the STF sequence is carried on all subcarriers of a plurality of consecutive RUs, the plurality of consecutive RUs are consecutive RUs corresponding to the distributed RU, and each of the consecutive RUs includes a plurality of subcarriers that are consecutive in frequency domain.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Bo GONG, Chenchen LIU, Mengshi HU, Jian YU, Ming GAN
  • Publication number: 20240091170
    Abstract: Provided are catechol nanoparticles, catechol protein nanoparticles, and a preparation method and use thereof. The method includes: adding a tannin compound-containing natural herb medicine into water to obtain a mixture, and subjecting the mixture to heating reflux extraction to obtain a herb medicine extract and subjecting the herb medicine extract to fractionation to obtain the catechol nanoparticles.
    Type: Application
    Filed: August 1, 2023
    Publication date: March 21, 2024
    Applicant: Shihezi University
    Inventors: Bo HAN, Jingmin Fan, Hang Yu, Rui Xue, Jiawei Guan, Yu Xu, Linyun He, Ji Liu, Chengyu Jiang, Xin Lu, Xiangze Kong, Wei Yu, Wen Chen
  • Publication number: 20240092920
    Abstract: The present disclosure relates to a dual inhibiting antibody that targets human interleukin-4 and interleukin-13, a manufacturing method therefor and use thereof.
    Type: Application
    Filed: June 29, 2023
    Publication date: March 21, 2024
    Applicant: Keymed Biosciences Co., Ltd.
    Inventors: Bo CHEN, Gang Xu, Juntao Yu
  • Publication number: 20240097842
    Abstract: A method includes: A station receives a trigger frame from an access point. The trigger frame is used to trigger the station to perform EHT TB PPDU transmission, the trigger frame further indicates a resource unit allocated to the station, and the trigger frame includes first indication information indicating that the station can perform EHT TB PPDU transmission on a portion of the allocated resource unit. The station sends an EHT TB PPDU based on an indication of the first indication information.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Yuxin LU, Ming GAN, Jian YU, Yunbo LI, Chenchen LIU, Bo GONG
  • Publication number: 20240093604
    Abstract: A method for determining a productivity of a coalbed methane well without shutting down the well includes steps of: obtaining coalbed methane basic data; based on PVT experimental data, determining a relationship table between a pressure and a coalbed methane deviation factor, and a relationship table between the pressure and a pseudo-pressure; recording daily gas production rates, bottomhole flow pressures, and cumulative gas productions at each stabilized flow pressure test moment in at least three different production stages; determining formation pressures corresponding to each stabilized flow pressure test moment based on a material balance equation; according to the formation pressures, the bottomhole flow pressures and the production rates, determining coefficients in a deliverability equation of the coalbed methane well for determining the deliverability equation; substituting the formation pressures and the bottomhole flow pressures into the deliverability equation for obtaining corresponding product
    Type: Application
    Filed: December 3, 2023
    Publication date: March 21, 2024
    Inventors: Bo Hu, Xiaobo Liu, Yongyi Zhou, Kui Chen, Yongming He, Linsong Liu, Yaonan Yu, Jiawei Zhang, Yongheng Wang
  • Publication number: 20240097010
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20240096388
    Abstract: A memory cell includes a read word line extending in a first direction, a write transistor, and a read transistor coupled to the write transistor. The read transistor includes a ferroelectric layer, a drain terminal of the read transistor directly connected to the read word line, and a source terminal of the read transistor coupled to a first node. The write transistor is configured to adjust a polarization state of the read transistor, the polarization state corresponding to a stored data value of the memory cell.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Inventors: Bo-Feng YOUNG, Sai-Hooi YEONG, Chao-I WU, Chih-Yu CHANG, Yu-Ming LIN
  • Publication number: 20240094411
    Abstract: A global positioning system (GPS)-bias detection and reduction system including a GPS-bias model having GPS statistical data creating a database representing data collected from a vehicle group having thousands or multiple thousands of vehicles saved in a database. At least one newly collected vehicle GPS data point is compared to the GPS statistical data to reduce negative effects of GPS-bias and to update the vehicle GPS-bias correction based on a previous GPS-bias model. A selected road node and a segment of a roadway have a map matching performed using a nearest service from a collection location of the GPS statistical data. A GPS-bias is calculated using a look-up of the database. An estimated horizontal position error (EHPE) defining a quality indicator is applied to distinguish a good quality GPS statistical data from a poor quality GPS statistical data.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Inventors: Gui Chen, Shu Chen, Bo Yu, Joon Hwang, Carl P. Darukhanavala, Vivek Vijaya Kumar
  • Publication number: 20240096782
    Abstract: A packaging device includes a first circuit substrate and a second circuit substrate that are electrically connected. The first circuit substrate includes a first line layer and a first insulation layer that are sequentially stacked, and a first electronic component is disposed on the first circuit substrate. The second circuit substrate includes a second line layer and a second insulation layer that are sequentially stacked, and a second electronic component is disposed on the second circuit substrate. A thermal conductivity of the first insulation layer is higher than a thermal conductivity of the second insulation layer. This application further provides a packaging module and an electronic device in which the packaging device is used. The packaging device in this application, the first insulation layer and the second insulation layer with different thermal conductivities are targetedly configured, and layouts of the first circuit substrate and the second circuit substrate are flexible.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 21, 2024
    Inventors: Bo Yu, Xudong Wang, Xin Li
  • Patent number: 11935257
    Abstract: An apparatus comprising an interface, a structured light projector and a processor. The interface may receive pixel data. The structured light projector may generate a structured light pattern. The processor may process the pixel data arranged as video frames, perform operations using a convolutional neural network to determine a binarization result and an offset value and generate disparity and depth maps in response to the video frames, the structured light pattern, the binarization result, the offset value and a removal of error points. The convolutional neural network may perform a partial block summation to generate a convolution result, compare the convolution result to a speckle value to determine the offset value, generate an adaptive result in response to performing a convolution operation, compare the video frames to the adaptive result to generate the binarization result for the video frames, and remove the error points from the binarization result.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: March 19, 2024
    Assignee: Ambarella International LP
    Inventors: Liangliang Wang, Wenhai Gao, Bo Yu
  • Patent number: 11935335
    Abstract: A system within an ego vehicle for robust association of a physical identity and a virtual identity of a target vehicle includes a data processor, including a wireless communication module and a visible light communication module, positioned within an ego vehicle, and a plurality of perception sensors, positioned within the ego vehicle and adapted to collect data related to a physical identity of the target vehicle and to communicate the data related to the physical identity of the target vehicle to the data processor via a communication bus, the data processor within the ego vehicle adapted to receive, via a wireless communication channel, data related to a virtual identity of the target vehicle, associate the physical identity of the target vehicle with the virtual identity of the target vehicle, and initiate, via the wireless communication channel and a visible light communication channel, a challenge-response protocol between the ego vehicle and the target vehicle.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: March 19, 2024
    Assignee: GM GLOBAL TECHNOLOY OPERATIONS LLC
    Inventors: Mohamed A. Layouni, Bo Yu, Markus Jochim