Patents by Inventor Bo Yu

Bo Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240067768
    Abstract: A waterborne polyurethane acrylate emulsion, comprising the following raw material components: a polyurethane acrylate prepolymer and a polyurethane acrylate oligomer. After ultraviolet curing, the waterborne polyurethane acrylate emulsion exhibits excellent mechanical strength and good wear resistance. The matt coatings produced therefrom has a fine matt fineness after curing.
    Type: Application
    Filed: December 24, 2021
    Publication date: February 29, 2024
    Inventors: Bo LV, Yuping WANG, Ligang YU, Fuliang PENG
  • Publication number: 20240063758
    Abstract: Wireless circuitry can have an antenna connected to a transmitting amplifier and a receiving amplifier. The wireless circuitry may be operable in a transmit mode during which only the transmitting amplifier is active and in a receive mode during which only the receiving amplifier is active. The transmitting amplifier may be connected to the antenna via a balun and a radio-frequency coupler without an intervening switch that is enabled during the transmit mode and disabled during the receive mode. The transmitting amplifier may include input transistors, cascode transistors, first switches configured to selectively decouple gate terminals of the cascode transistors from a bias voltage, output capacitors, and second switches configured to selectively decouple the output capacitors from a ground line. The first and second switches are turned on during the transmit mode and are turned off during the receive mode to increase an output impedance of the transmitting amplifier.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Inventors: Nitesh Singhal, Bo Yu, Kefei Wu
  • Publication number: 20240063759
    Abstract: Wireless circuitry can have an antenna connected to a transmitting amplifier and a receiving amplifier. The wireless circuitry may be operable in a transmit mode during which only the transmitting amplifier is active and in a receive mode during which only the receiving amplifier is active. The transmitting amplifier may be connected to the antenna via a balun and a radio-frequency coupler without an intervening switch that is enabled during the transmit mode and disabled during the receive mode. The transmitting amplifier may include input transistors, cascode transistors, first switches configured to selectively decouple gate terminals of the cascode transistors from a bias voltage, output capacitors, and second switches configured to selectively decouple the output capacitors from a ground line. The first and second switches are turned on during the transmit mode and are turned off during the receive mode to increase an output impedance of the transmitting amplifier.
    Type: Application
    Filed: September 13, 2023
    Publication date: February 22, 2024
    Inventors: Nitesh Singhal, Bo Yu, Kefei Wu
  • Patent number: 11901408
    Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.
    Type: Grant
    Filed: February 15, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sai-Hooi Yeong, Feng-Cheng Yang, Yih-Ann Lin, Yen-Ming Chen
  • Publication number: 20240047397
    Abstract: A semiconductor device includes a substrate, one or more wiring layers disposed over the substrate, a passivation layer disposed over the one or more wiring layers, a first conductive layer disposed over the passivation layer, a second conductive layer disposed over the first conductive layer, an isolation structure formed in the first and second conductive layers to isolate a part of the first and second conductive layers, and a first metal pad disposed over the isolation structure and the part of the first and second conductive layers. In one or more of the foregoing or following embodiments, the semiconductor device further includes a second metal pad disposed over the second conductive layer and electrically isolated from the first metal pad.
    Type: Application
    Filed: March 20, 2023
    Publication date: February 8, 2024
    Inventors: Bo-Yu CHIU, Pei-Wei LEE, Fu Wei LIU, Yun-Chung WU, Hao Chun YANG, Chin-Yu KU, Ming-Da CHENG, Ming-Ji LII
  • Patent number: 11891401
    Abstract: The application relates to N-(4-fluoro-3-(6-(3-methylpyridin-2-yl)-[1,2,4]triazolo[1,5-a]pyrimidin-2-yl)phenyl)-2,4-dimethyloxazole-5-carboxamide (Compound I) fumaric acid co-crystals and X-ray amorphous complexes of Compound (I) and fumaric acid. The application also provides methods of making the same; pharmaceutical compositions comprising them; and their use in treating, preventing, inhibiting, ameliorating, or eradicating the pathology and/or symptomology of a disease caused by a kinetoplastid parasite, such as leishmaniasis, human African trypanosomiasis and Chagas disease.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: February 6, 2024
    Assignee: NOVARTIS AG
    Inventors: Yudong Cao, Siyi Jiang, Hongyong Kim, Andreas Kordikowski, Irene Xia, Bo Yu, Jing Zhang, Yi Zhao
  • Patent number: 11888081
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface, an optical device disposed on the first surface of the substrate, and an electronic device disposed on the second surface of the substrate. A power of the electronic device is greater than a power of the optical device. A vertical projection of the optical device on the first surface is spaced apart from a vertical projection of the electronic device on the second surface by a distance greater than zero.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Yi Wu, Chang Chin Tsai, Bo-Yu Huang, Ying-Chung Chen
  • Publication number: 20240030724
    Abstract: In accordance with an embodiment, and energy storage system includes a battery cluster, a power conversion circuit, and a controller. An output end of the battery cluster is connected to a first terminal of the power conversion circuit, and a second terminal of the power conversion circuit is connected to an output end of the energy storage system. Each battery cluster includes at least two energy storage modules connected in series, each energy storage module includes one bypass circuit and one battery pack, and each battery pack includes a plurality of batteries. The controller controls each bypass circuit based on a first parameter value of each battery pack, so that electricity quantities of battery packs are balanced.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 25, 2024
    Inventors: Lin Li, Zhipeng Wu, Bo Yu
  • Publication number: 20240031852
    Abstract: This application provides a service processing method and apparatus, a terminal device, and a chip, and relates to the field of communication technologies. When the terminal device carries a primary card and a secondary card, the secondary card uses one or more antennas by default to process an uplink/downlink transmission service. When the primary card is triggered to perform neighboring cell measurement (e.g., inter-frequency inter-RAT measurement), and a measurement band is the same as an operating band of the secondary card, the primary card may select an antenna different from an antenna used by the secondary card to perform neighboring cell measurement.
    Type: Application
    Filed: December 8, 2021
    Publication date: January 25, 2024
    Inventors: Jian Jiang, Bo Yu, Qiang Yu
  • Patent number: 11881518
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: January 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Publication number: 20240021698
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 18, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsien-Wen WAN, Yi-Ting CHENG, Ming-Hwei HONG, Juei-Nai KWO, Bo-Yu YANG, Yu-Jie HONG
  • Publication number: 20240021890
    Abstract: This application discloses a battery system and an energy storage container. The battery system includes a plurality of battery packs that are connected in series. Each battery pack corresponds to one first switch that is connected in series to the battery pack. Each battery pack corresponds to one second switch that is connected in parallel to the battery pack. Each battery pack is connected in series to the corresponding first switch and then connected in parallel to the second switch. The first switch includes a plurality of controllable switching transistors that are connected in parallel. The second switch includes a plurality of controllable switching transistors that are connected in parallel. The plurality of controllable switching transistors included in the first switch correspond to at least two different turn-on moments. The plurality of controllable switching transistors included in the second switch correspond to at least two different turn-on moments.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Inventors: Jianshan Li, Bo Yu, Bo Li
  • Patent number: 11865891
    Abstract: A system for active roll control for a vehicle body is provided and includes a sensor operable to monitor a tilt of the body and a suspension system. The suspension system includes an active sway bar including a first bar portion, a second bar portion, and an active roll control motor disposed between the first bar portion and the second bar portion. The active roll control motor is operable to turn the first bar portion in relation to the second bar portion. The system further includes a computerized active roll control controller which is operative to monitor a driving mode including one of straight-line driving and rounding a curve on a road, monitor an output of the sensor, determine a desired roll moment based upon the driving mode and the output of the sensor, and control the active roll control motor based upon the desired roll moment.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: January 9, 2024
    Assignee: GM Global Technology Operations LLC
    Inventors: Robert G. Izak, Nojan Medinei, Larry G. Gepfrey, Bo Yu
  • Publication number: 20240006113
    Abstract: An inductor includes a coil, a conductive lead frame, and a housing. The coil includes a coil body and a lead protruding from the coil body. The lead has a U-bend portion. The lead is electrically fixed onto the conductive lead frame. The housing encapsulates the coil and exposes the conductive lead frame. A method of manufacturing an inductor includes the following steps: providing a coil, providing a conductive lead frame, making a lead of the coil be electrically fixed onto the conductive lead frame, bending the lead to form a U-bend portion and make the main body of the coil close to a portion of the lead that connects with the conductive lead frame, and forming a housing to encapsulate the coil and expose the conductive lead frame.
    Type: Application
    Filed: June 4, 2023
    Publication date: January 4, 2024
    Applicant: DARFON ELECTRONICS CORP.
    Inventors: Zuei-Chown Jou, Chih-Ho Liu, Jui-Wen Kuo, Chi-Ming Huang, Bo-Yu Huang, Yao-Tsung Chen
  • Publication number: 20240006525
    Abstract: A method for manufacturing a high electron mobility transistor device includes providing a substrate. A channel material, a barrier material, a polarization adjustment material and a conductive material are formed on the substrate. A hard mask layer is formed on the conductive material. The conductive material is patterned to form a conductive layer by using the hard mask layer as a mask. A plurality of protection layers is formed on sidewalls of the hard mask layer and the conductive layer. The polarization adjustment material is patterned to form a polarization adjustment layer by using the plurality of protection layers and the hard mask as masks. The plurality of protection layers is removed. A portion of the conductive layer is laterally removed to form a first gate conductive layer.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 4, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Yuan Yu Chung, Bo-Yu Chen, You-Jia Chang, Lung-En Kuo, Kun-Yuan Liao, Chun-Lung Chen
  • Patent number: 11862713
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20230418285
    Abstract: A method for performing a plurality of vehicle computing tasks includes determining the plurality of vehicle computing tasks that need to be performed and monitoring a wireless connectivity between a vehicle and a remote computing system. Monitoring the wireless connectivity between the vehicle and the remote computing system includes measuring, in real time, at least one quality of service (QoS) measurement of the wireless connectivity between the vehicle and the remote computing system. The method further includes determining whether to perform at least one of the plurality of vehicle computing tasks in at least one of the remote computing system or a vehicle controller of the vehicle based on at least one QoS measurement.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Inventors: Markus Jochim, Fan Bai, Bo Yu, Yuchen Zhou
  • Patent number: 11855097
    Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Yu Lai, Kai-Hsuan Lee, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Patent number: 11855182
    Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Kai Lin, Bo-Yu Lai, Li Chun Te, Kai-Hsuan Lee, Sai-Hooi Yeong, Tien-I Bao, Wei-Ken Lin
  • Patent number: 11852671
    Abstract: A photovoltaic energy system and a method for detecting a ground insulation impedance, improve accuracy of detecting a ground insulation impedance after one or more conversion circuits are connected in parallel. The photovoltaic energy system includes one or more conversion circuits and a detection circuit. The detection circuit includes an alternating current signal source and a sampling resistor that are connected in series, a first sampling circuit, and a control circuit. The control circuit is configured to control the alternating current signal source to output harmonic signals of a first frequency and a second frequency. The first sampling circuit is configured to: when the alternating current signal source outputs the harmonic signal of the first frequency, collect a voltage at both terminals of the sampling resistor to obtain a first voltage.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: December 26, 2023
    Assignee: HUAWEI DIGITAL POWER TECHNOLOGIES CO., LTD.
    Inventors: Zhong Wang, Shengjie Zhang, Jianshan Li, Yu Peng, Shijiang Yu, He Zhou, Bo Yu