Abstract: The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 ?m pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a first rigid substrate, a second rigid substrate, a flexible substrate comprising a first portion attached to the first rigid substrate, a second portion attached to the second rigid substrate, a middle portion connecting the first portion to the second portion, wherein the middle portion is bent, and metallic traces therethrough, and a component forming a direct interface with the middle portion of the flexible substrate, the component electrically coupled to the metallic traces. In selected examples, the device further includes a casing.

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a first substrate including a first surface, an opposing second surface and a recess opening extending through the first surface. The electronic assembly may also include a power delivery mold frame including a first mold surface, an opposing second mold surface, a plurality of first metal planes and a plurality of second metal planes extending between the first and second mold surfaces, the power delivery mold frame arranged in the recess opening and coupled to the first substrate through the first mold surface. The electronic assembly may further include a second substrate including a subsequent first surface, an opposing subsequent second surface, the second substrate coupled to the power delivery mold frame through a plurality of first solder bumps and further coupled to the first substrate through a plurality of second solder bumps at the subsequent first surface.

Abstract: Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.

Abstract: The present disclosure is directed generally to semiconductor packages, semiconductor package substrates, and methods for making them, which include packages substrates with embedded passive devices positioned between plated through hole vias configured for an improved power delivery network.

Abstract: Foldable Compression Attached Memory Modules (fCAMMs) and associated apparatus, assemblies and systems. The fCAMM comprises a compression contact module having a plurality of contact means arranged in one or more arrays on its underside, first and second fold modules including multiple memory devices, and flexible interconnects coupling the compression contact module to the first and second fold modules. Under one assembled configuration, portions of printed circuit boards (PCBs) for the first and second fold modules are folded over portions of the compression contact module. Under another configuration, the first fold module is disposed above the second fold module, which is disposed above the compression contact module. In an assembly or system including a motherboard, a compression mount technology (CMT) connector or a land grid array (LGA) assembly is disposed between the motherboard and the compression contact module. Bolster plates are used to urge the compression contact module toward the motherboard.

Abstract: The present disclosure is directed to a semiconductor package including: a package substrate including a top surface, lateral sides and a bottom surface; a ball grid array including a plurality of solder balls coupled to the bottom surface; a stiffener including a bottom portion affixed to the bottom surface of the package substrate and a lateral portion extending from the bottom portion and affixed to the lateral sides of the package substrate, the bottom portion of the stiffener including a plurality of openings for the plurality of solder balls, wherein the top surface of the package substrate is substantially flush with a top surface of the lateral portion; and an electronic component coupled to the top surface of the package substrate.

Abstract: The present disclosure relates to an electronic assembly including a package substrate with a first surface and an opposing second surface; a first interconnect disposed in the package substrate and extending between the first and the second surfaces; and a second interconnect disposed in the package substrate and extending between the first and the second surfaces; wherein the first interconnect comprises a first recessed side wall and the second interconnect is arranged adjacent the first recessed side wall.

Abstract: The present disclosure generally relates to a printed circuit board assembly that may include a circuit board having a first surface and an opposing second surface. The printed circuit board assembly may also include a first interconnect barrel disposed in the circuit board. The first interconnect barrel may have a first length extending between the first surface and the second surface. The first interconnect barrel may include a first section, and may further include a second section spaced apart from the first section by a first gap having a first depth extending partially through the first length. The printed circuit board assembly may further include a first conductive trace coupled to the first section and a second conductive trace coupled to the second section at a first terminal.

Abstract: The present disclosure is directed to multichip semiconductor packages, and methods for making them, which includes a package substrate with an integrated bridge frame having a first horizontal portion positioned on a top surface of the package substrate, with first and second dies positioned overlapping the first horizontal portion of the bridge frame, and a second horizontal portion positioned on the bottom surface of the package substrate, with third and fourth dies positioned overlapping the second horizontal portion of the bridge frame. The bridge frame further includes first and second vertical portions separated by a portion of the package substrate positioned under the first horizontal portion of the bridge frame between the top surface and bottom surfaces of the package substrate, and a plurality of vertical interconnects adjacent to the first and second vertical portions of the bridge frame.

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

Abstract: According to various examples, a device is described. The device may include a stiffener member including a first step section and a second step section. The device may also include a plurality of vias extending from or through the stiffener member. The device may be coupled to a printed circuit board.

Abstract: According to various examples, a stacked semiconductor package is described. The stacked semiconductor package may include a package substrate. The stacked semiconductor package may also include a base die disposed on and electrically coupled to the package substrate. The stacked semiconductor package may further include a mold portion disposed on the package substrate at a periphery of the base die, the mold portion may include a through-mold interconnect electrically coupled to the package substrate. The stacked semiconductor package may further include a semiconductor device having a first section disposed on the base die and a second section disposed on the mold portion, wherein the second section of the semiconductor device may be electrically coupled to the package substrate through the through-mold interconnect.

Abstract: Disclosed embodiments include frame-array interconnects that have a ledge portion to accommodate a passive device. A seated passive device is between at least two frame-array interconnects for semiconductor package-integrated decoupling capacitors.

Abstract: A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.

Abstract: The present disclosure relates to a semiconductor package that may include a substrate. The substrate may have a top surface and a bottom surface. The semiconductor package may include an opening in the substrate. The semiconductor package may include a bridge disposed in the opening. The bridge may have an upper end at the top surface of the substrate and a lower end at the bottom surface of the substrate. The semiconductor package may include a first die on the top surface of the substrate at least partially extending over a first portion of the upper end of the bridge. The semiconductor package may include a second die on the bottom surface of the substrate at least partially extending over the lower end of the bridge. The bridge may couple the first die to the second die.

Abstract: A multiple-damascene structure is located below a semiconductor device footprint on a printed wiring board, where the structure includes multiple recesses that containing useful devices coupled to a semiconductive device.