Patents by Inventor Boon Bing NG
Boon Bing NG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10340011Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.Type: GrantFiled: December 21, 2017Date of Patent: July 2, 2019Inventors: Boon Bing Ng, Hang Ru Goy
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Publication number: 20190156892Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.Type: ApplicationFiled: January 23, 2019Publication date: May 23, 2019Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Publication number: 20190152234Abstract: Examples of a printhead assembly comprising an Erasable Programmable Read-only Memory (EPROM) having a predefined number of banks, with EPROM cells arranged in rows and columns in each of the banks are described. In one example, the printhead assembly comprises a shift register to generate, in consecutive shift register cycles, a row select signal, column select signal, and bank select signal to select a row, column, and bank, respectively, corresponding to an EPROM cell. A row select signal bus, column select signal bus and bank select signal bus is included in the printhead assembly to provide the row select signal, column select signal, and bank select signal, respectively, to the EPROM cell during the respective shift register cycles.Type: ApplicationFiled: July 15, 2016Publication date: May 23, 2019Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Jerrin Pathrose Vareed, Boon Bing Ng
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Patent number: 10236063Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.Type: GrantFiled: May 22, 2018Date of Patent: March 19, 2019Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Patent number: 10224935Abstract: A device having ratioed logic with a high impedance load is described. The device includes a pull-down network coupled between a first voltage and an output. The device also includes a high impedance load coupled between a second voltage and the output. The high impedance load being smaller than a transistor of the pull-down network.Type: GrantFiled: October 30, 2014Date of Patent: March 5, 2019Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Ning Ge, Boon Bing Ng, Leong Yap Chia
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Publication number: 20190001695Abstract: A print head has a fluid slot and a sensing chamber having a first port connected to the fluid slot and a second port. The sensing chamber contains an ink level sensor. A circulation passage extends from the fluid slot and is fluidly coupled to the second port. A fluid pump circulates fluid through the circulation passage.Type: ApplicationFiled: September 8, 2018Publication date: January 3, 2019Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Alexander Govyadinov, Adam L. Ghozeil, Boon Bing Ng, Patrick Leonard, Raymond Connolly
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Patent number: 10155379Abstract: A fluid ejection device including a printhead die having a plurality of layers, including a single metal layer, and having an integrated ink level sensor. The ink level sensor includes an ink chamber above the metal layer, a metal plate of a sense capacitor disposed in the metal layer, and a clearing resistor circuit disposed in the metal layer including four clearing resistors arranged in a surround-4 configuration about the metal plate and electrically connected in parallel between a voltage potential and ground, wherein adjacent ends of at least two clearing resistors are not directly connected to one another so as to leave a gap between the adjacent ends in the metal layer. A metal lead in the metal layer extends through the gap to the metal plate.Type: GrantFiled: October 29, 2014Date of Patent: December 18, 2018Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Boon Bing Ng, Hang Ru Goy, Patrick Leonard, Shane O'Brien
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Publication number: 20180354271Abstract: The present subject matter relates to printhead-integrated ink level sensor (PILS) system. In an example implementation, the PILS system includes a sense capacitor plate in a fluid sensing chamber to sense a level of fluid in the fluid sensing chamber. The fluid sensing chamber is in fluid communication with a fluid reservoir of the printhead to receive fluid from the fluid reservoir. The sense capacitor plate includes at least one slot. The PILS system further includes at least one central clearing resistor and at least one peripheral clearing resistor to clear the fluid sensing chamber of the fluid. The central clearing resistor is provided in the at least one slot of the sense capacitor plate. The at least one peripheral resistor is provided in the fluid sensing chamber surrounding the sense capacitor plate.Type: ApplicationFiled: November 10, 2015Publication date: December 13, 2018Applicant: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Patrick Leonard, Raymond Connolly
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Patent number: 10099484Abstract: A print head has an ink slot and a sensing chamber having a first port connected to the fluid slot and a second port. The sensing chamber contains an ink level sensor. A recirculation passage extends from the fluid slot and is fluidly coupled to the second port. A fluid pump circulates fluid through the recirculation passage.Type: GrantFiled: October 30, 2014Date of Patent: October 16, 2018Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Alexander Govyadinov, Adam L Ghozeil, Boon Bing Ng, Patrick Leonard, Raymond Connolly
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Publication number: 20180268905Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.Type: ApplicationFiled: May 22, 2018Publication date: September 20, 2018Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Patent number: 10029457Abstract: A nozzle firing cell may comprise a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge line and a gate of the firing transistor wherein the pre-charge line is routed over the gate of the pre-charge transistor. A fluid ejection device may comprise a circuit comprising a nozzle firing cell, the nozzle firing cell comprising a firing transistor and a pre-charge transistor having a source and drain coupled between a pre-charge Sine and a gate of the firing transistor in which the pre-charge line is routed over the gate of the pre-charge transistor. A circuit may comprise a number of firing transistors and a number of pre-charge transistors each having a source and drain coupled between a pre-charge line and a gate of one of the firing transistors in which the pre-charge line is routed over each of the gates of the pre-charge transistors.Type: GrantFiled: July 30, 2014Date of Patent: July 24, 2018Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Publication number: 20180186151Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.Type: ApplicationFiled: March 2, 2018Publication date: July 5, 2018Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Jose Jehrome Rando
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Patent number: 10014055Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.Type: GrantFiled: July 30, 2014Date of Patent: July 3, 2018Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Ning Ge, Jose Jehrome Rando
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Patent number: 9975335Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.Type: GrantFiled: August 18, 2014Date of Patent: May 22, 2018Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Thida Ma Win, Jose Jehrome Rando
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Publication number: 20180114579Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.Type: ApplicationFiled: December 21, 2017Publication date: April 26, 2018Applicant: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing NG, Hang Ru GOY
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Patent number: 9928912Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.Type: GrantFiled: April 17, 2017Date of Patent: March 27, 2018Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Bing Ng, Hang Ru Goy
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Publication number: 20180006045Abstract: The present subject matter relates to an electrical programmable read only memory (EPROM) cell. The EPROM cell comprises a semiconductor substrate and a floating gate separated from the semiconductor substrate by a first dielectric layer. A control gate is capacitively coupled to the floating gate through a second dielectric layer disposed between the floating gate and the control gate. In an example, the EPROM cell further comprises a conductive gate connected to the floating gate, wherein the conductive gate is to leak charges from the floating gate in a predetermined leak time period.Type: ApplicationFiled: January 29, 2015Publication date: January 4, 2018Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Boon Bing Ng, Lui Cheat Thin, Reynaldo V Villavelez
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Patent number: 9849672Abstract: An example provides a fluid ejection apparatus including a first firing resistor and a second firing resistor to selectively cause fluid to be ejected through a single nozzle, and a parasitic resistor arranged to add a parasitic resistance to the first firing resistor.Type: GrantFiled: April 3, 2014Date of Patent: December 26, 2017Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ning Ge, Hang-Ru Goy, Boon Bing Ng, Shane O'Brien, Mun Hooi Yaow
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Publication number: 20170317680Abstract: A device having ratioed logic with a high impedance load is described. The device includes a pull-down network coupled between a first voltage and an output. The device also includes a high impedance load coupled between a second voltage and the output. The high impedance load being smaller than a transistor of the pull-down network.Type: ApplicationFiled: October 30, 2014Publication date: November 2, 2017Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Ning Ge, Boon Bing Ng, Leong Yap Chia
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Publication number: 20170313093Abstract: A print head has an ink slot and a sensing chamber having a first port connected to the fluid slot and a second port. The sensing chamber contains an ink level sensor. A recirculation passage extends from the fluid slot and is fluidly coupled to the second port. A fluid pump circulates fluid through the recirculation passage.Type: ApplicationFiled: October 30, 2014Publication date: November 2, 2017Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Alexander Govyadinov, Adam L Ghozeil, Boon Bing Ng, Patrick Leonard, Raymond Connolly