Patents by Inventor Bor Chiuan Hsieh
Bor Chiuan Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180350906Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.Type: ApplicationFiled: July 24, 2018Publication date: December 6, 2018Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
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Publication number: 20180315830Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.Type: ApplicationFiled: August 2, 2017Publication date: November 1, 2018Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
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Patent number: 10084040Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.Type: GrantFiled: October 11, 2016Date of Patent: September 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
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Publication number: 20170194424Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.Type: ApplicationFiled: October 11, 2016Publication date: July 6, 2017Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
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Patent number: 9437712Abstract: A method embodiment includes forming a protective liner over the substrate and forming an inter-layer dielectric over the protective liner. The protective liner covers a sidewall of a gate spacer. The method further includes patterning a contact opening in the first ILD to expose a portion of the protective liner. The portion of the protective liner in the contact opening is removed to expose an active region at a top surface of the semiconductor substrate. A contact is formed in the contact opening. The contact is electrically connected to the active region.Type: GrantFiled: March 7, 2014Date of Patent: September 6, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Tai-Chun Huang, Chia-Ying Lee, Tze-Liang Lee
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Patent number: 9218974Abstract: An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.Type: GrantFiled: June 7, 2013Date of Patent: December 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao
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Publication number: 20150255275Abstract: A method embodiment includes forming a protective liner over the substrate and forming an inter-layer dielectric over the protective liner. The protective liner covers a sidewall of a gate spacer. The method further includes patterning a contact opening in the first ILD to expose a portion of the protective liner. The portion of the protective liner in the contact opening is removed to expose an active region at a top surface of the semiconductor substrate. A contact is formed in the contact opening. The contact is electrically connected to the active region.Type: ApplicationFiled: March 7, 2014Publication date: September 10, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Tai-Chun Huang, Chia-Ying Lee, Tze-Liang Lee
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Publication number: 20150125591Abstract: Systems and methods for supplying a precursor material for an atomic layer deposition (ALD) process are provided. A gas supply provides one or more precursor materials to a deposition chamber. The deposition chamber receives the one or more precursor materials via an input line. A gas circulation system is coupled to an output line of the deposition chamber. The gas circulation system includes a gas composition detection system configured to produce an output signal indicating a composition of a gas exiting the deposition chamber through the output line. The gas circulation system also includes a circulation line configured to transport the gas exiting the deposition chamber to the input line. A controller is coupled to the gas supply. The controller controls the providing of the one or more precursor materials by the gas supply based on the output signal of the gas composition detection system.Type: ApplicationFiled: November 5, 2013Publication date: May 7, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: BOR-CHIUAN HSIEH, CHIEN-KUO HUANG, TAI-CHUN HUANG, KUANG-YUAN HSU, TZE-LIANG LEE
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Patent number: 8999834Abstract: An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.Type: GrantFiled: February 20, 2014Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao
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Patent number: 8900956Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.Type: GrantFiled: November 22, 2013Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
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Patent number: 8900957Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.Type: GrantFiled: November 22, 2013Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
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Publication number: 20140170846Abstract: An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.Type: ApplicationFiled: February 20, 2014Publication date: June 19, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao
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Publication number: 20140073097Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.Type: ApplicationFiled: November 22, 2013Publication date: March 13, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
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Publication number: 20140073096Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.Type: ApplicationFiled: November 22, 2013Publication date: March 13, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
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Patent number: 8609497Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.Type: GrantFiled: March 10, 2010Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
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Publication number: 20130270651Abstract: An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.Type: ApplicationFiled: June 7, 2013Publication date: October 17, 2013Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao
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Patent number: 8299508Abstract: A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.Type: GrantFiled: April 9, 2010Date of Patent: October 30, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Bor Chiuan Hsieh, Han-Ping Chung, Chih-Hsin Ko, Bor-Wen Chan, Hun-Jan Tao
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Publication number: 20110201164Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming first and second gate structures over first and second regions of a substrate, respectively, forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material, forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, forming a protection layer over the second region to protect the second gate structure, removing the capping layer over the first gate structure; removing the protection layer over the second region, epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region, and removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material.Type: ApplicationFiled: March 10, 2010Publication date: August 18, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Ming-Jie Huang
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Patent number: 7947551Abstract: An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed to extend from the top surface into the substrate. The trench has sidewalls and a bottom surface. A silicon liner layer is formed on the sidewalls and the bottom surface. A flowable dielectric material is filled in the trench. An anneal process is performed to densify the flowable dielectric material and convert the silicon liner layer into a silicon oxide layer simultaneously.Type: GrantFiled: September 28, 2010Date of Patent: May 24, 2011Inventors: Sen-Hong Syue, Bor Chiuan Hsieh, Shiang-Bau Wang
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Publication number: 20110084355Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an isolation feature disposed on the substrate, and an active area disposed adjacent the isolation feature. The isolation feature may be a shallow trench isolation feature. The STI feature has a first width at the top of the feature and a second width at the bottom of the feature. The first width is less than the second width. Methods of fabricating a semiconductor device is also provided. A method includes forming shallow trench isolation features and then growing an epitaxial layer adjacent the STI features to form an active region.Type: ApplicationFiled: October 9, 2009Publication date: April 14, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsien-Hsin Lin, Bor Chiuan Hsieh, Chen-Ping Chen