Patents by Inventor Bor Chiuan Hsieh

Bor Chiuan Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CMOS STRUCTURE WITH MULTIPLE SPACERS
    Publication number: 20110031538
    Abstract: A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.
    Type: Application
    Filed: April 9, 2010
    Publication date: February 10, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bor Chiuan HSIEH, Han-Ping CHUNG, Chih-Hsin KO, Bor-Wen CHAN, Hun-Jan TAO
  • Sidewall-Free CESL for Enlarging ILD Gap-Fill Window
    Publication number: 20100314690
    Abstract: An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.
    Type: Application
    Filed: March 30, 2010
    Publication date: December 16, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Pin Chung, Bor Chiuan Hsieh, Shiang-Bau Wang, Hun-Jan Tao