Abstract: Split data error correction code (ECC) circuits including a control circuit coupled to an error correction code (ECC) circuit. The ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access. The split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access.

Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.

Abstract: One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written to a page in the memory device has encoded therein an expected count value corresponding to the number of times a first binary value occurs in the data pattern. The data pattern includes the program data and the expected count value, and is written to the page in a single operation. The expected count value may be stored in a count field in the management area of the page. During a page read operation, the expected count value is compared to the actual count of the number of bits having the first binary value in the data area of the page. If the expected count is equal to the actual count, then the program data is determined to be valid.

Abstract: One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written to a page in the memory device has encoded therein an expected count value corresponding to the number of times a first binary value occurs in the data pattern. The data pattern includes the program data and the expected count value, and is written to the page in a single operation. The expected count value may be stored in a count field in the management area of the page. During a page read operation, the expected count value is compared to the actual count of the number of bits having the first binary value in the data area of the page. If the expected count is equal to the actual count, then the program data is determined to be valid.

Abstract: One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written to a page in the memory device has encoded therein an expected count value corresponding to the number of times a first binary value occurs in the data pattern. The data pattern includes the program data and the expected count value, and is written to the page in a single operation. The expected count value may be stored in a count field in the management area of the page. During a page read operation, the expected count value is compared to the actual count of the number of bits having the first binary value in the data area of the page. If the expected count is equal to the actual count, then the program data is determined to be valid.

Abstract: A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the memory device to a first location of a memory of the memory device is stopped. First data that remains in the register after the program failure is detected is transferred to a second location of the memory. At the second location of the memory, the first data is combined with second data from the first location of the memory that remains in the first location of the memory after the program failure is detected to reconstruct third data that was originally intended to be programmed in the first location before the program failure was detected.

Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.

Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.

Abstract: A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the memory device to a first location of a memory of the memory device is stopped. First data that remains in the register after the program failure is detected is transferred to a second location of the memory. At the second location of the memory, the first data is combined with second data from the first location of the memory that remains in the first location of the memory after the program failure is detected to reconstruct third data that was originally intended to be programmed in the first location before the program failure was detected.

Abstract: A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the memory device to a first location of a memory of the memory device is stopped. First data that remains in the register after the program failure is detected is transferred to a second location of the memory. At the second location of the memory, the first data is combined with second data from the first location of the memory that remains in the first location of the memory after the program failure is detected to reconstruct third data that was originally intended to be programmed in the first location before the program failure was detected.

Abstract: One or more techniques are provided for programming a flash memory device. In one embodiment, the memory device is programmed such that a data pattern written to a page in the memory device has encoded therein an expected count value corresponding to the number of times a first binary value occurs in the data pattern. The data pattern includes the program data and the expected count value, and is written to the page in a single operation. The expected count value may be stored in a count field in the management area of the page. During a page read operation, the expected count value is compared to the actual count of the number of bits having the first binary value in the data area of the page. If the expected count is equal to the actual count, then the program data is determined to be valid.

Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.

Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.

Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.

Abstract: A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the memory device to a first location of a memory of the memory device is stopped. First data that remains in the register after the program failure is detected is transferred to a second location of the memory. At the second location of the memory, the first data is combined with second data from the first location of the memory that remains in the first location of the memory after the program failure is detected to reconstruct third data that was originally intended to be programmed in the first location before the program failure was detected.

Abstract: Methods and apparatus are provided. A method of operating a memory device includes detecting a programming failure at a first location of a memory array, preserving data within the memory device when the program failure is detected, programming a second location of the memory array with a first portion of the preserved data, programming a third location of the memory array with a second portion of the preserved data, and combining, at the second location of the memory array, the first portion of the preserved data programmed in the second location of the memory array with a third portion of the preserved data from the first location of the memory array.

Abstract: A method of operating a memory device when a program failure occurs is provided.

Abstract: Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in combination with a stored record of known flaws, errors, or questionable data bits of a read memory row or block to allow for more efficient processing and correction of these errors. An embodiment of the present invention utilizes an erasure pointer that can store the location of N bad or questionable bits in the memory segment that is currently being read, where for each bit stored by the erasure pointer the embodiment also contains 2N ECC generators to allow the read data to be quickly checked with the know bad bits in each possible state. This allows the read data to then be easily corrected on the fly before it is transferred by selecting the bad bit state indicated by the ECC generator detecting an uncorrupted read.

Abstract: Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.

Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.