Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.

Abstract: Provided is a method for assigning register tags to instructions at issue time. The method comprises receiving an instruction for execution by a microprocessor. The method further comprises dispatching the instruction to an issue queue without assigning a register tag to the instruction. The method further comprises determining that the instruction is ready to issue. In response to determining that the instruction is ready to issue, the method comprises assigning an available register tag to the instruction. The method further comprises issuing the instruction.

Abstract: In at least one embodiment, a processor includes architected and non-architected register files for buffering operands. The processor additionally includes an instruction fetch unit that fetches instructions to be executed and at least one execution unit. The at least one execution unit is configured to execute a first class of instructions that access operands in the architected register file and a second class of instructions that access operands in the non-architected register file. The processor also includes a mapper circuit that assigns physical registers to the instructions for buffering of operands. The processor additionally includes a dispatch circuit configured, based on detection of an instruction in one of the first and second classes of instructions for which correct operands do not reside in a respective one of the architected and non-architected register files, to automatically initiate transfer of operands between the architected and non-architected register files.

Abstract: A system, processor, and/or technique configured to: determine whether two or more load instructions are fusible for execution in a load store unit as a fused load instruction; in response to determining that two or more load instructions are fusible, transmit information to process the two or more fusible load instructions into a single entry of an issue queue; issue the information to process the two or more fusible load instructions from the single entry in the issue queue as a fused load instruction to the load store unit using a single issue port of the issue queue, wherein the fused load instruction contains the information to process the two or more fusible load instructions; execute the fused load instruction in the load store unit; and write back data obtained by executing the fused load instruction simultaneously to multiple entries in the register file.

Abstract: Load store addressing can include a processor, which fuses two consecutive instruction determined to be prefix instructions and treats the two instructions as a single fused instruction. The prefix instruction of the fused instruction is auto-finished at dispatch time in an issue unit of the processor. A suffix instruction of the fused instruction and its fields and the prefix instruction's fields are issued from an issue queue of the issue unit, wherein an opcode of the suffix instruction is issued to a load store unit of the processor, and fields of the fused instruction are issued to the execution unit of the processor. The execution unit forms operands of the suffix instruction, at least one operand formed based on a current instruction address of the single fused instruction. The load store unit executes the suffix instruction using the operands formed by the execution unit.

Abstract: A system, processor, and/or technique configured to: determine whether two or more load instructions are fusible for execution in a load store unit as a fused load instruction; in response to determining that two or more load instructions are fusible, transmit information to process the two or more fusible load instructions into a single entry of an issue queue; issue the information to process the two or more fusible load instructions from the single entry in the issue queue as a fused load instruction to the load store unit using a single issue port of the issue queue, wherein the fused load instruction contains the information to process the two or more fusible load instructions; execute the fused load instruction in the load store unit; and write back data obtained by executing the fused load instruction simultaneously to multiple entries in the register file.

Abstract: A system and method for avoiding write back collisions. The system receives a plurality of instructions at a pipeline queue. Next an issue queue determines a number of cycles for each instruction of the plurality of instructions. The issue queue further determines if a collision will occur between at least two of the instructions. Additionally, the system determines in response to a collision between at least two of the instructions, a number of cycles to delay at least one of the at least two instructions. The instructions are then executed. The system then places the results of the instruction for instructions that had a calculated delay in a result buffer for the determined number of cycles of delay. After the determined number of cycles of delay, the system sends the results to a results mux. Once received at the results mux the results are written back to the register file.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor, a register file associated with the at least one processor, preferably a condition register that stores status information, the register file having multiple locations for storing data, multiple ports to write data to and read data from the register file. The system or processor includes an execution area, and the processor is configured to read from all the read ports in a first cycle, and to read from all the read ports in a second cycle. In an embodiment, the execution area includes a staging latch to store data from a first cycle read operation, and in an aspect the computer system is configured to combine the data stored in the staging latch during a first read cycle with the data read from the second cycle.

Abstract: A method, processor and/or system for processing data is disclosed that in an aspect includes providing a physical register file with one or more register file entries for storing data; identifying each physical register file entry with a row identifier to identify the entry row in the physical register file; enabling one or more columns within a target entry row of the physical register file; and revising data in the columns enabled within the target entry row of the physical register file. In an aspect, each physical register file entry is partitioned into a plurality of columns having a bit width and a column mask preferably is used to enable the one or more columns within the target row of the physical register file, and data is revised in only the columns enabled by the column mask.

Abstract: Support for instruction fusion is provided. An indication whether an instruction is a paired instruction is received from an instruction decoder. Based on the indication, one dispatch slot or a paired dispatch slot is allocated in the instruction dispatcher queue. A mapper converts logical addresses of sources and targets of the instruction to physical addresses. Either one issue slot or a paired issue slot is allocated in an issue queue based on the indication from the instruction decoder. The instruction execution environment is loaded into the issue queue and issued to an execution unit.

Abstract: In at least one embodiment, a processor includes architected register file and non-architected register files for buffering operands. The processor additionally includes an instruction fetch unit that fetches instructions to be executed and at least one execution unit. The at least one execution unit is configured to execute a first class of instructions that access operands in the architected register file and a second class of instructions that access operands in the non-architected register file. The processor also includes a mapper circuit that assigns physical registers to the instructions for buffering of operands. The processor additionally includes a dispatch circuit configured, based on detection of an instruction in one of the first and second classes of instructions for which correct operands do not reside in a respective one of the architected and non-architected register files, to automatically initiate transfer of operands between the architected and non-architected register files.

Abstract: Technology for fusing an add-immediate instruction with a load-immediate instruction (or store-immediate instruction) in a microprocessor. This can result in quicker address generation while performing a load and store operation.

Abstract: Recovering microprocessor logical register values by: partitioning a register mapper by logical register type; providing a plurality of recovery ports; assigning a logical register type to a recovery port; receiving a restore required instruction; and mapping SRB (save and restore buffer) values to the register mapper by logical register type.

Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number “N” of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.

Abstract: A non-limiting example of a computer-implemented method for file register writes using pointers includes, responsive to a dispatch instruction, storing, at a location in a history buffer, an instruction tag and first data associated with the instruction tag. The method further includes storing a pointer in an issue queue. The pointer points to the location in the history buffer. The method further includes performing a write back of second data using the pointer stored in the issue queue. The write back writes the second data into the location of the history buffer associated with the pointer.

Abstract: An aspect includes receiving a flush request at a processing unit that is in a current state defined by contents of registers in a register file. The processing unit includes a plurality of slices and the flush request includes an identifier of a previously issued instruction. The processing unit is restored to a previous state defined by contents of the registers in the register file prior to the previously issued instruction being issued. The restoring includes searching previous state buffers in at least two of the plurality of slices to locate data describing the contents of the registers in the register file prior to the previously issued instruction being issued. The restoring also includes combining the located data to generate results of the searching and updating the contents of the registers in the register file using a single port based at least in part on the results.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number “N” of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.