Abstract: A method, processor and system for processing data is disclosed that includes evicting one or more evicted fields from a logical register mapper; receiving, by a history buffer, the one or more evicted fields from the logical register mapper; determining whether two or more of the evicted fields from the mapper qualify to be written to a single entry in the history buffer; and in response to the two or more evicted fields qualifying, writing the two or more qualifying evicted fields received from the mapper to a single entry in the qualified history buffer. The method, processor, and/or system further includes in an embodiment, remapping the one or more qualified evicted fields, and further, in response to the two or more evicted fields not qualifying to be written to a single entry in the history buffer, writing the two or more evicted fields to multiple history buffer entries.

Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.

Abstract: Techniques are disclosed for performing issue queue snooping for an asynchronous flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying an entry of the HB to restore to a register file in the processing unit. A restore ITAG of the HB entry is sent to the register file via a first restore bus, and restore data of the HB entry and the restore ITAG is sent to the register file via a second restore bus. After the restore ITAG and restore data are sent, an instruction is dispatched before the register file obtains the restore data. After it is determined that the restore data is still available via the second restore bus, a snooping operation is performed to obtain the restore data from the second restore bus for the dispatched instruction.

Abstract: A multi-slice processor comprising a high-level structure and history buffer. Write backs are no longer associated with the history buffer and the history buffer comprises slices determined by logical register allocation. The history buffer receives a register pointer entry and either releases or restores the entry with functional units comprised in the history buffer.

Abstract: A computer system, processor, and method for processing information is disclosed that includes a Dispatch Unit for dispatching instructions; an Issue Queue for receiving instructions dispatched from the Dispatch Unit; and a queue for receiving instructions issued from the Issue Queue, the queue having a plurality of entry locations for storing data. In an embodiment instructions are dispatched with a virtual indicator, and the virtual indicator is set to a first mode for instructions dispatched where an entry location is available, and to a second mode where an entry location is not available, in the queue to receive the dispatched instruction. In addition to virtual tagging dispatched instructions, a system, processor, and method are disclosed for regional partitioning of queues, region based deallocation of queue entries, and circular thread based assignment of queue entries.

Abstract: A method, processor and system for processing data is disclosed that includes evicting one or more evicted fields from a logical register mapper; receiving, by a history buffer, the one or more evicted fields from the logical register mapper; determining whether two or more of the evicted fields from the mapper qualify to be written to a single entry in the history buffer; and in response to the two or more evicted fields qualifying, writing the two or more qualifying evicted fields received from the mapper to a single entry in the qualified history buffer. The method, processor, and/or system further includes in an embodiment, remapping the one or more qualified evicted fields, and further, in response to the two or more evicted fields not qualifying to be written to a single entry in the history buffer, writing the two or more evicted fields to multiple history buffer entries.

Abstract: A method, processor and/or system for processing data is disclosed that in an aspect includes providing a physical register file with one or more register file entries for storing data; identifying each physical register file entry with a row identifier to identify the entry row in the physical register file; enabling one or more columns within a target entry row of the physical register file; and revising data in the columns enabled within the target entry row of the physical register file. In an aspect, each physical register file entry is partitioned into a plurality of columns having a bit width and a column mask preferably is used to enable the one or more columns within the target row of the physical register file, and data is revised in only the columns enabled by the column mask.

Abstract: An aspect includes receiving a flush request at a processing unit that is in a current state defined by contents of registers in a register file. The processing unit includes a plurality of slices and the flush request includes an identifier of a previously issued instruction. The processing unit is restored to a previous state defined by contents of the registers in the register file prior to the previously issued instruction being issued. The restoring includes searching previous state buffers in at least two of the plurality of slices to locate data describing the contents of the registers in the register file prior to the previously issued instruction being issued. The restoring also includes combining the located data to generate results of the searching and updating the contents of the registers in the register file using a single port based at least in part on the results.

Abstract: A non-limiting example of a computer-implemented method for file register writes using pointers includes, responsive to a dispatch instruction, storing, at a location in a history buffer, an instruction tag and first data associated with the instruction tag. The method further includes storing a pointer in an issue queue. The pointer points to the location in the history buffer. The method further includes performing a write back of second data using the pointer stored in the issue queue. The write back writes the second data into the location of the history buffer associated with the pointer.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor for processing instructions, the processor having a history buffer having a plurality of entries for storing information associated with a processor instruction evicted from a logical register, the history buffer having at least one recovery port; a logical register mapper for recovering information from the history buffer, the mapper having restore ports to recover information from the history buffer; and a restore multiplexor configured to receive as inputs information from one or more of the history buffer recovery ports, and configured to output information to one or more of the logical register mapper restore ports. The processor, system and/or method configured to improve flush recovery bandwidth.

Abstract: Recovering microprocessor logical register values by: partitioning a register mapper by logical register type; providing a plurality of recovery ports; assigning a logical register type to a recovery port; receiving a restore required instruction; and mapping SRB (save and restore buffer) values to the register mapper by logical register type.

Abstract: Embodiments herein describe a reservation station (RS) in a processor that merges control data from multiple sources into a merged control data value. Before an instruction issues, the RS gathers and saves control data indicating how the instruction is to be executed. This control data may be saved in control registers. An instruction, however, can update many different types of status control bits in these registers. As such, the RS may store different types of control data for an instruction. Instead of the RS containing multiple registers and data paths for every type of control data, the embodiments herein describe merge logic in the RS that permits control data from different sources to be merged into a single control data value. Once the instruction is issued, the RS passes the merged control data value to an execution unit for processing.

Abstract: A multi-slice processor comprising a high-level structure and history buffer. Write backs are no longer associated with the history buffer and the history buffer comprises slices determined by logical register allocation. The history buffer receives a register pointer entry and either releases or restores the entry with functional units comprised in the history buffer.

Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.

Abstract: A computer system, processor, and method for processing information is disclosed that includes reading out a plurality of entries in a history buffer prior to initiating a flush recovery process; initiating the flush recovery process; determining which of the history buffer entries read out of the history buffer should be recovered; and sending information associated with the history buffer entries to be recovered to one or more history buffer recovery ports. In one or more embodiments, the history buffer entries are continually read out in response to a processor and history buffer entries read out from the history buffer are directed to a specific history buffer recovery port associated with a mapper of a specific logical register.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor for processing instructions, the processor having a history buffer having a plurality of entries for storing information associated with a processor instruction evicted from a logical register, the history buffer having a at least one recovery port; a logical register mapper for recovering information from the history buffer, the mapper having restore ports to recover information from the history buffer; and a restore multiplexor configured to receive as inputs information from one or more of the history buffer recovery ports, and configured to output information to one or more of the logical register mapper restore ports. The processor, system and/or method configured to improve flush recovery bandwidth.

Abstract: A microprocessor has a data-less history buffer. Operands associated with a program instructions are stored in logical registers (LREGs) which are resolvable to physical registers that are not part of the history buffer. Register re-naming maintains integrity of data dependencies for instructions processed out of program order. The history buffer has pointers (RTAGs) to the LREGs. Entries in the history buffer are grouped into ranges. A mapper has a single port associated with each LREG, and each port receives data, from a single range of entries in the history buffer. Multiple entries, one from each range, may be restored concurrently from the history buffer to the mapper.

Abstract: A computer system, processor, and method for processing information is disclosed that includes a Dispatch Unit for dispatching instructions; an Issue Queue for receiving instructions dispatched from the Dispatch Unit; and a queue for receiving instructions issued from the Issue Queue, the queue having a plurality of entry locations for storing data. In an embodiment instructions are dispatched with a virtual indicator, and the virtual indicator is set to a first mode for instructions dispatched where an entry location is available, and to a second mode where an entry location is not available, in the queue to receive the dispatched instruction. In addition to virtual tagging dispatched instructions, a system, processor, and method are disclosed for regional partitioning of queues, region based deallocation of queue entries, and circular thread based assignment of queue entries.

Abstract: Embodiments include systems, methods, and computer program products for using a multi-level history buffer (HB) for a speculative transaction. One method includes after dispatching a first instruction indicating start of the speculative transaction, marking one or more register file (RF) entries as pre-transaction memory (PTM), and after dispatching a second instruction targeting one of the marked RF entries, moving data from the marked RF entry to a first level HB entry and marking the first level HB entry as PTM. The method also includes upon detecting a write back to the first level HB entry, moving data from the first level HB entry to a second level HB entry and marking the second level HB entry as PTM. The method further includes upon determining that the second level HB entry has been completed, moving data from the second level HB entry to a third level HB entry.

Abstract: A split level history buffer in a central processing unit is provided. The history buffer includes first, second, and third levels, each having different characteristics. Operational instructions are provided to support the split history buffer. A first instruction is fetched, tagged, and stored in an entry of a register file. As a second instruction is fetched and tagged, the first instruction is evicted from the register file and stored in the first level of the history buffer. Similarly, as a result for the first instruction is generated, the first instruction and the generated result are stored in the second level of the history buffer. In response to instruction completion, instead of remaining in the second level, the first instruction, which contains pre-transactional memory checkpoint data, is moved from the second level to the third level of the history buffer, together with pre-transactional memory data, and the first instruction entry in the second level is invalidated.