Patents by Inventor Brian Leibowitz
Brian Leibowitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9148322Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.Type: GrantFiled: October 28, 2011Date of Patent: September 29, 2015Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly, Brian Leibowitz
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Patent number: 9137063Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.Type: GrantFiled: January 20, 2006Date of Patent: September 15, 2015Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly, Brian Leibowitz
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Patent number: 9083280Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.Type: GrantFiled: August 5, 2014Date of Patent: July 14, 2015Assignee: Rambus Inc.Inventors: Brian Leibowitz, Hae-Chang Lee, Farshid Aryanfar, Kun-Yung Chang, Jie Shen
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Publication number: 20150092898Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.Type: ApplicationFiled: December 8, 2014Publication date: April 2, 2015Inventors: Hae-Chang Lee, Brian Leibowitz, Jaeha Kim, Jafar Savoj
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Publication number: 20150078495Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.Type: ApplicationFiled: March 13, 2012Publication date: March 19, 2015Applicant: Rambus Inc.Inventors: Masum Hossain, Brian Leibowitz, Jihong Ren
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Patent number: 8929496Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.Type: GrantFiled: January 30, 2009Date of Patent: January 6, 2015Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Brian Leibowitz, Jaeha Kim, Jafar Savoj
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Publication number: 20140340120Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.Type: ApplicationFiled: August 5, 2014Publication date: November 20, 2014Inventors: Brian Leibowitz, Hae-Chang Lee, Farshid Aryanfar, Kun-Yung Chang, Jie Shen
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Publication number: 20140293710Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.Type: ApplicationFiled: October 26, 2012Publication date: October 2, 2014Applicant: RAMBUS INC.Inventors: Frederick A. Ware, Ely Tsern, Brian Leibowitz, Jared Zerbe
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Publication number: 20140169438Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.Type: ApplicationFiled: August 29, 2013Publication date: June 19, 2014Applicant: Rambus Inc.Inventors: Qi Lin, Brian Leibowitz, Hae-Chang Lee, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe
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Patent number: 8618869Abstract: Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.Type: GrantFiled: December 30, 2011Date of Patent: December 31, 2013Assignee: Rambus Inc.Inventors: Wayne Dettloff, John Wilson, Lei Luo, Brian Leibowitz, Jared Zerbe, Pravin Kumar Venkatesan
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Patent number: 8548110Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.Type: GrantFiled: December 13, 2007Date of Patent: October 1, 2013Assignee: Rambus Inc.Inventors: Qi Lin, Brian Leibowitz, Hae-Chang Lee, Jihong Ren, Kyung Suk Oh, Jared Zerbe
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Publication number: 20130093433Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.Type: ApplicationFiled: September 17, 2012Publication date: April 18, 2013Applicant: RAMBUS INC.Inventors: Hae-Chang Lee, Jaeha Kim, Brian Leibowitz
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Patent number: 8289032Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.Type: GrantFiled: March 19, 2008Date of Patent: October 16, 2012Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Jaeha Kim, Brian Leibowitz
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Publication number: 20120218001Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.Type: ApplicationFiled: October 31, 2010Publication date: August 30, 2012Applicant: RAMBUS INC.Inventors: Brian Leibowitz, Hae-Chang Lee, Farshid Aryanfar, Kun-Yung Chang, Jie Shen
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Publication number: 20120207196Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.Type: ApplicationFiled: April 20, 2012Publication date: August 16, 2012Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly, Brian Leibowitz
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Publication number: 20120169412Abstract: Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.Type: ApplicationFiled: December 30, 2011Publication date: July 5, 2012Applicant: Rambus Inc.Inventors: Wayne Dettloff, John Wilson, Lei Luo, Brian Leibowitz, Jared Zerbe, Pravin Kumar Venkatesan
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Patent number: 8198930Abstract: A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary.Type: GrantFiled: October 27, 2010Date of Patent: June 12, 2012Assignee: Rambus Inc.Inventors: Jared Zerbe, Brian Leibowitz, Lei Luo, John Wilson, Anshuman Bhuyan, Marko Aleksic
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Publication number: 20120087452Abstract: A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.Type: ApplicationFiled: May 31, 2010Publication date: April 12, 2012Applicant: RAMBUS INC.Inventors: Jared Zerbe, Pradeep Batra, Brian Leibowitz
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Publication number: 20120044984Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.Type: ApplicationFiled: October 28, 2011Publication date: February 23, 2012Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly, Brian Leibowitz
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Publication number: 20110310949Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.Type: ApplicationFiled: August 23, 2011Publication date: December 22, 2011Applicant: Rambus Inc.Inventors: Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly, Brian Leibowitz