Abstract: Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.

Abstract: Apparatus for identifying stable physically unclonable function (PUF) cells includes an array of PUF cells, a bias control circuit, and a selector circuit. The bias control circuit has a plurality of bias control lines that apply one or more bias control signals to each PUF cell in the array of PUF cells. The selector circuit selects a subset of the PUF cells in the array of PUF cells based on whether outputs of the PUF cells in the array of PUF cells change in response to application of the bias control signals. A corresponding method is also disclosed.

Abstract: Systems and methods for partially reconfiguring a programmable IC device are presented. Processing circuitry on the programmable IC device may identify a first region of the IC device to be reconfigured from a received bitstream. The processing circuitry may read a configuration bit associated with the identified first region, and determine, based on the configuration bit, whether to permit the received bitstream to reconfigure the identified first region. The received bitstream may be authenticated using an authentication key from a first set of authentication keys. The processing circuitry may determine whether to permit the received bitstream to reconfigure the identified first region based on the authentication key and the configuration bit.

Abstract: A Physically Unclonable Function circuit may include precharge circuitry that precharges an output. The precharge circuitry may include transistors of a first type such as N-type or P-type. Circuitry having only transistors of a second, different type may be coupled to the output. The circuitry may produce a signal at the output based on variations between the transistors of the second type. The circuitry may include first and second circuits such as first and second transistors of the second type that are cross-coupled. While the circuitry is producing the signal at the output, the precharge circuitry or any transistors not of the second type may be disabled or electrically disconnected from the output. In this way, the stability over time of the Physically Unclonable Function circuit may be improved, because only variations associated with transistors of the second type may be used in producing the signal.

Abstract: Methods and systems are provided for securely authenticating data of an integrated circuit. By authenticating data having keystream blocks inserted between ciphertext portions, it becomes more difficult to mount successful authentication-based attacks.

Abstract: A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL.

Abstract: In an exemplary embodiment, an apparatus includes a first set of circuit elements and a second set of circuit elements. The first set of circuit elements is used in a first configuration of the apparatus, and the second set of circuit elements is used in a second configuration of the apparatus. The first configuration of the apparatus is switched to the second configuration of the apparatus in order to improve reliability of the apparatus.

Abstract: Systems and methods relating to generating a key that is difficult to clone are described. The methods include receiving a programmable logic device (PLD) with a first key and applying a one-way hash function to a second key or the first key and the second key to create a third key. The application of the one-way hash function is performed using one or more components hardwired into the PLD. The methods further include storing the third key in the PLD only after using the one or more components to apply the one-way hash function.

Abstract: Methods and systems are provided for securing an integrated circuit device against various security attacks, such as side-channel attacks. By limiting the number of different challenge vectors that can be combined with a critical variable of an encryption operation, it becomes more difficult to create enough side channel measurements to successfully perform statistical side-channel analysis.

Abstract: Systems and methods are disclosed for reducing or eliminating address lines that need to be routed to multiple related embedded memory blocks. In particular, one or more inputs are added to a block Random Access Memory (RAM) such that when one or more of the inputs are asserted, the address input to the Block RAM may be incremented prior to being used to retrieve data contents of the block RAM. Thus, if address <addr> is provided to the block RAM and the address increment signal is asserted, data may be read from location <addr+N> instead of <addr>, where N may be an integer. Block RAMs with such address arithmetic may be used to implement wide First-In-First-Out (FIFO) queues, wide memories, and/or data-burst accessible block RAMs.

Abstract: Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates from an expected signal. Fault detection circuits may also be configured to identify instances where two or more or N or more signals deviate from an expected signal. Mechanisms may also be provided to assure the reliability of fault detection circuitry itself.

Abstract: Circuits, methods, and systems are provided for securing an integrated circuit device against Differential Power Analysis (DPA) attacks. Plaintext (e.g., configuration data for a programmable device) may be encrypted in an encryption system using a cryptographic algorithm. Ciphertext may be decrypted in a decryption system using the cryptographic algorithm. The encryption and/or decryption systems may obfuscate the plaintext, the ciphertext, and/or the substitution tables used by the cryptographic algorithm. The encryption and/or decryption systems may also generate cryptographic key schedules by using different keys for encrypting/decrypting different blocks and/or by expanding round keys between encryption/decryption blocks. These techniques may help mitigate or altogether eliminate the vulnerability of cryptographic elements revealing power consumption information to learn the value of secret information, e.g., through DPA.

Abstract: Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates from an expected signal. Fault detection circuits may also be configured to identify instances where two or more or N or more signals deviate from an expected signal. Mechanisms may also be provided to assure the reliability of fault detection circuitry itself.

Abstract: Circuitry and methods prevent unauthorized programming, or reprogramming, of a programmable device, by requiring a signature in the configuration data to match a signature previously stored in the programmable device. A programmable integrated circuit device includes an input for configuration data, and programming control circuitry operable to derive a current signature from the configuration data, examine a first bit stored in the programmable integrated circuit device, and when the first bit is in a first state, compare the current signature to a first predetermined signature stored in the programmable integrated circuit device and configure the programmable integrated circuit device according to the configuration data only when the current signature matches the first predetermined signature, and when the first bit is in a second state, configure the programmable integrated circuit device according to the configuration data without comparing the current signature to the first predetermined signature.

Abstract: Apparatus for identifying stable physically unclonable function (PUF) cells includes an array of PUF cells, a bias control circuit, and a selector circuit. The bias control circuit has a plurality of bias control lines that apply one or more bias control signals to each PUF cell in the array of PUF cells. The selector circuit selects a subset of the PUF cells in the array of PUF cells based on whether outputs of the PUF cells in the array of PUF cells change in response to application of the bias control signals. A corresponding method is also disclosed.

Abstract: Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates from an expected signal. Fault detection circuits may also be configured to identify instances where two or more or N or more signals deviate from an expected signal. Mechanisms may also be provided to assure the reliability of fault detection circuitry itself.

Abstract: On-die variability noise or other variations in the power supply voltage to a storage circuit may cause the ability to perform memory access operations to be marginal. A control circuit may be coupled to the storage circuit and the power distribution network and monitor the actual power supply voltage. The control circuit may include a reference voltage generator that generates a nominal voltage. The control circuit may further include a comparator that generates a status signal based on a comparison between the actual power supply voltage and a nominal voltage. Based on the status signal, the control circuit may control memory access operations performed by the storage circuit. For example, the control circuit may enable and disable the execution of read and write operations on the storage circuit. If desired, the control circuit may also control the operation of predetermined portions of the integrated circuit.

Abstract: Techniques of the present invention impede power consumption measurements of an encryption engine on a logic device by running the encryption engine with an independent clock. This clock produces a signal that is decoupled from and asynchronous to clock signals feeding other circuits on the device. The clock feeding the encryption engine is not accessible externally to the device. Circuits may be employed to intentionally slow down or add jitter to one or more of the clock signals.

Abstract: A Physically Unclonable Function circuit may include precharge circuitry that precharges an output. The precharge circuitry may include transistors of a first type such as N-type or P-type. Circuitry having only transistors of a second, different type may be coupled to the output. The circuitry may produce a signal at the output based on variations between the transistors of the second type. The circuitry may include first and second circuits such as first and second transistors of the second type that are cross-coupled. While the circuitry is producing the signal at the output, the precharge circuitry or any transistors not of the second type may be disabled or electrically disconnected from the output. In this way, the stability over time of the Physically Unclonable Function circuit may be improved, because only variations associated with transistors of the second type may be used in producing the signal.

Abstract: A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may be implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD.