Abstract: Integrated circuits with memory error detection and correction (EDC) circuitry are provided. The EDC circuitry may include first and second data registers and a comparator. The first data register may store data read from a selected frame. The second data register may be loaded with a predetermined bit stream. If a soft error is detected, correct bits generated using a logic function associated with the predetermined bit stream may be written back to the selected frame. In another suitable arrangement, the EDC circuitry may include first and second registers, a mask register, and a comparator. The first data register may store data read from a selected frame. The second data register may be loaded with desired data. The mask register may be loaded with mask bits. If a soft error is detected, the correct bits may be written back to the selected frame if the corresponding mask bits are high.

Abstract: Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain. A plurality of respective scan enable activation elements controls a respective subplurality of the plurality of control elements for connecting a respective subplurality of the plurality of memory elements into the scan chain. Each scan enable activation element is actuated, to connect its respective subplurality of the plurality of memory elements into the scan chain, by a first enable signal common to more than one of the scan enable activation elements, and a second enable signal for that one of the scan enable activation elements. Such scan chain circuitry may be used for entering configuration data into a programmable integrated circuit device.

Abstract: Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain. A plurality of respective scan enable activation elements controls a respective subplurality of the plurality of control elements for connecting a respective subplurality of the plurality of memory elements into the scan chain. Each scan enable activation element is actuated, to connect its respective subplurality of the plurality of memory elements into the scan chain, by a first enable signal common to more than one of the scan enable activation elements, and a second enable signal for that one of the scan enable activation elements. Such scan chain circuitry may be used for entering configuration data into a programmable integrated circuit device.

Abstract: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

Abstract: Techniques for reconfiguring an integrated circuit (IC) are provided. The techniques may improve error detection in the partially reconfigurable IC. A cyclic redundancy check (CRC) value for a first configuration data is received by the IC and a second configuration data is generated based on the first configuration data and a prior configuration data stored in the IC. The first configuration data may be a partial reconfiguration data that is used to reconfigure at least a portion of the IC. A third configuration data is then generated based on the first and second configuration data and the prior configuration data. A second CRC value is calculated based on the third configuration data. The second CRC value, together with the first CRC value and a prior CRC value stored in the IC, is used to calculate an updated CRC value. The updated CRC value is stored in the IC.

Abstract: Techniques of the present invention impede power consumption measurements of an encryption engine on a logic device by running the encryption engine with an independent clock. This clock produces a signal that is decoupled from and asynchronous to clock signals feeding other circuits on the device. The clock feeding the encryption engine is not accessible externally to the device. Circuits may be employed to intentionally slow down or add jitter to one or more of the clock signals.

Abstract: Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.

Abstract: Circuits and methods for verifying the unique identity, or digital fingerprint, of an integrated circuit (IC) are presented. The complete circuit is located inside the IC to avoid external tampering and includes a random number generator (RNG), a key register, an encryption circuit, and selection circuitry. The key register stores an encryption key generated by the RNG during the initialization phase. The encryption key can be read from the outside of the IC solely during the initialization phase. After the initialization phase, the encryption circuit generates a response to a challenge using the encryption key, and the selection circuitry outputs in a pin of the IC the response to the challenge. The response is used to check the unique ID of the IC. The encryption key is never sent to the outside of the IC after initialization, and mimicking the behavior of the IC by an impostor is avoided by the use of the encryption mechanism.

Abstract: Systems and methods are disclosed for allowing security features to be selectively enabled during device configuration. For example, a programmable integrated circuit device is provided that receives configuration data and security requirement data. Control circuitry compares enabled security features in the device against the security requirements, and can configure the programmable integrated circuit device with the configuration data or prevent such configuration. Control circuitry may also use the security requirement data to set security features within the device.

Abstract: Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as FPGAs, have two stages of operation; a configuration stage and a user mode stage. To prevent tampering and/or reverse engineering of a programmable device, various anti-tampering techniques may be employed during either stage of operation to disable the device and/or erase sensitive information stored on the device once tampering is suspected. One type of tampering involves bombarding the device with a number of false configuration attempts in order to decipher encrypted data. By utilizing a dirty bit and a sticky error counter, the device can keep track of the number of failed configuration attempts that have occurred and initiate anti-tampering operations when tampering is suspected while the device is still in the configuration stage of operation.

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.

Abstract: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

Abstract: A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of physical inputs.

Abstract: Systems and methods are disclosed for securing a programmable integrated circuit device against an over-voltage attack. Generally, programmable devices, such as FPGAs, contain volatile memory registers that may store sensitive information. To prevent tampering and/or reverse engineering of such a programmable device, an over-voltage detection circuit may be employed to disable the device and/or erase the sensitive information stored on the device when an over-voltage attack is suspected. In particular, once the over-voltage detection circuit detects that the voltage applied to the programmable device exceeds a trigger voltage, it may cause logic circuitry to erase the sensitive information stored on the device. Desirably, the over-voltage detection circuit includes components arranged in such a way as to render current consumption negligible when the voltage applied to the programmable device, e.g., by a battery, remains below the trigger voltage.

Abstract: Systems and methods are provided for destroying or erasing circuitry elements, data, or both, such as transistors, volatile keys, or fuse blocks, located in an integrated circuit device. An initiation signal may be provided to induce latch-up in a circuitry element in response to a user command, a tampering event, or both. As a result of the latch-up effect, the circuitry element, data, or both may be destroyed or erased.

Abstract: A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors.

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.

Abstract: A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may he implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD.

Abstract: Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates from an expected signal. Fault detection circuits may also be configured to identify instances where two or more or N or more signals deviate from an expected signal. Mechanisms may also be provided to assure the reliability of fault detection circuitry itself.

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected to form a bistable element. Clear lines such as true and complement clear lines may be routed to positive power supply terminals and ground power supply terminals associated with certain transistor pairs. During clear operations, some or all of the transistor pairs can be selectively depowered using the clear lines. This facilitates clear operations in which logic zero values are driven through the address transistors and reduces cross-bar current surges.