Abstract: Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip (i.e., the TIM has an essentially symmetric shape and does not extend vertically along the sidewalls of the chip). Also, disclosed herein are embodiments of a method of forming such an electronic package that uses a hierarchical heating process that cures a lid sealant, thereby securing the lid to the substrate, and then reflows (i.e., melts and cools) the TIM, thereby adhering the TIM to both the chip and lid. This hierarchical heating process ensures that the TIM has the above-mentioned characteristics (i.e., a predetermined minimum thickness and registration to the top surface of the chip) and further provides robust process windows for high-yield, low-cost electronic package manufacturing.

Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric is disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.

Abstract: An apparatus for cooling a surface having a metal structure made of a material with high thermal conductivity, and designed to provide efficient cooling of the surface while minimizing mechanical stress between the metal structure and the surface.

Abstract: An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.

Abstract: An electrical structure including a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.

Abstract: An electrical interconnect forming method. The electrical interconnect includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure, a first solder structure, and a second solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. The second solder structure electrically and mechanically connects a second portion of the non-solder metallic core structure to the second electrically conductive pad.

Abstract: The present invention is a patterned metal thermal interface. In one embodiment a system for dissipating heat from a heat-generating device includes a heat sink having a first surface adapted for thermal coupling to a first surface of the heat generating device and a thermal interface having at least one patterned surface, the thermal interface being adapted to thermally couple the first surface of the heat sink to the first surface of the heat generating device. The patterned surface of the thermal interface allows the thermal interface to deform under compression between the heat sink and the heat generating device, leading to better conformity of the thermal interface to the surfaces of the heat sink and the heat generating device.

Abstract: A cooling apparatus and method of fabrication are provided for facilitating removal of heat from a heat-generating electronic device. The method of fabrication includes: obtaining a solder material; disposing the solder material on a surface to be cooled; and reflowing and shaping the solder material disposed on the surface to be cooled to configure the solder material as a base with a plurality of fins extending therefrom. In addition to being in situ-configured on the surface to be cooled, the base is simultaneously metallurgically bonded to the surface to be cooled. The solder material, configured as the base with a plurality of fins extending therefrom, is a single, monolithic structure thermally attached to the surface to be cooled via the metallurgical bonding thereof to the surface to be cooled.

Abstract: A cooling apparatus and method of fabrication are provided for facilitating removal of heat from a heat-generating electronic device. The method of fabrication includes: obtaining a solder material; disposing the solder material on a surface to be cooled; and reflowing and shaping the solder material disposed on the surface to be cooled to configure the solder material as a base with a plurality of fins extending therefrom. In addition to being in situ-configured on the surface to be cooled, the base is simultaneously metallurgically bonded to the surface to be cooled. The solder material, configured as the base with a plurality of fins extending therefrom, is a single, monolithic structure thermally attached to the surface to be cooled via the metallurgical bonding thereof to the surface to be cooled.

Abstract: The present invention is a patterned metal thermal interface. In one embodiment a system for dissipating heat from a heat-generating device includes a heat sink having a first surface adapted for thermal coupling to a first surface of the heat generating device and a thermal interface having at least one patterned surface, the thermal interface being adapted to thermally couple the first surface of the heat sink to the first surface of the heat generating device. The patterned surface of the thermal interface allows the thermal interface to deform under compression between the heat sink and the heat generating device, leading to better conformity of the thermal interface to the surfaces of the heat sink and the heat generating device.

Abstract: A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

Abstract: A cooling apparatus and method of fabrication are provided for facilitating removal of heat from a heat-generating electronic device. The method of fabrication includes: obtaining a solder material; disposing the solder material on a surface to be cooled; and reflowing and shaping the solder material disposed on the surface to be cooled to configure the solder material as a base with a plurality of fins extending therefrom. In addition to being in situ-configured on the surface to be cooled, the base is simultaneously metallurgically bonded to the surface to be cooled. The solder material, configured as the base with a plurality of fins extending therefrom, is a single, monolithic structure thermally attached to the surface to be cooled via the metallurgical bonding thereof to the surface to be cooled.

Abstract: Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip (i.e., the TIM has an essentially symmetric shape and does not extend vertically along the sidewalls of the chip). Also, disclosed herein are embodiments of a method of forming such an electronic package that uses a hierarchical heating process that cures a lid sealant, thereby securing the lid to the substrate, and then reflows (i.e., melts and cools) the TIM, thereby adhering the TIM to both the chip and lid. This hierarchical heating process ensures that the TIM has the above-mentioned characteristics (i.e., a predetermined minimum thickness and registration to the top surface of the chip) and further provides robust process windows for high-yield, low-cost electronic package manufacturing.

Abstract: A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

Abstract: In one embodiment, the present invention is a method and apparatus for chip cooling. One embodiment of an inventive method for bonding a liquid metal to an interface surface (e.g., a surface of an integrated circuit chip or an opposing surface of a heat sink) includes applying an adhesive to the interface surface. A metal film is then bonded to the adhesive, thereby easily adapting the interface surface for bonding to the liquid metal.

Abstract: An electrical structure and method for forming. The electrical structure includes a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and an interconnect structure electrically and mechanically connecting the first electrically conductive pad to the second electrically conductive pad. The interconnect structure comprises a non-solder metallic core structure and a first solder structure. The first solder structure electrically and mechanically connects a first portion of the non-solder metallic core structure to the first electrically conductive pad. A second portion of the non-solder metallic core structure is thermo-compression bonded to the second electrically conductive pad.

Abstract: An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad.