Abstract: A system comprising: a first integrated circuit device having a multi-band transmission circuit; second and third integrated circuit devices having respective multi-band reception circuits; and a signaling link including a first stub coupled to the multi-band transmission circuit to receive a multi-band signal therefrom, second and third stubs coupled to the multi-band reception circuits of the second and third integrated circuit devices, respectively, to deliver the multi-band signal thereto, and a plurality of channel segments that extend between the first, second and third stubs to convey the multi-band transmission signal therebetween, and wherein at least one of a physical length, impedance or propagation constant of at least one of the first stub, second stub, third stub or channel segment of the plurality of channel segments is selected to spectrally position a frequency-interval exhibiting attenuated frequency response on the signaling link such that multiple passbands separated by the frequency-inter

Abstract: A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master device via the first bus and to transmit signals to the one or more slave devices via the second bus in response to the incoming signals, and a read buffer to receive outgoing signals from the one or more slave devices via the second bus and to transmit signals to the master device via the first bus in response to the outgoing signals.

Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.

Abstract: An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

Abstract: In a receive circuit within an integrated circuit device, a binary input signal is sampled in response to transitions of a sampling clock signal to generate a set of data samples. The binary input signal is additionally compared with first and second threshold levels to generate respective first and second edge samples. The phase of the sampling clock signal is adjusted based, at least in part, on the first edge sample if the set of data samples matches a first data pattern and based, at least in part, on the second edge sample if the set of data samples matches a second data pattern.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

Abstract: A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.

Abstract: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

Abstract: An integrated circuit device includes one or more calibration paths including one or more devices. A signal generator is coupled to at least one calibration path and configured to provide the calibration path with a calibration signal having known characteristics. A controller is coupled to the signal generator and the calibration path and configured to adjust the signal generator and at least one parameter associated with at least one device in the calibration path.

Abstract: A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Abstract: Described are approaches to routing buffered reference clock signals to a plurality of input/output (I/O) cell instances on an integrated circuit (IC) die. All or a subset of the I/O cell instances include clock routing resources optimized to deliver high-speed, low jitter clock signals within and through the particular instance. The clock routing resources in physically adjacent instances of the input/output cells for a given IC die automatically interconnect, collectively forming clock routing infrastructure optimized for groups of cell instances. This modular approach to clock routing simplifies the task of combining I/O cell instances with other I/O cell instances and with other types of circuitry.

Abstract: A receiver includes simple, effective margining circuitry to support manufacturer and in-situ margin testing of high-speed communication channels. The receiver includes an input pad coupled to a termination resistor and the input of a sampler. An internal or external current source alters the current through the termination resistor to vary the DC component of the input signal applied to the input of the sampler. The voltage margins of the receiver may be tested by monitoring the output of the sampler in response to a known data stream while adjusting the voltage on the input node of the sampler to determine the degree of voltage offset that can be tolerated without inducing receive errors.

Abstract: An integrated circuit includes clock synthesis and distribution circuitry that includes cascaded PLLs to deliver low-noise transmit and receive clock signals that can be tuned over a broad range of frequencies. The clock synthesis circuitry derives a low-jitter intermediate reference clock signal IRClk from a relatively noisy, low-frequency external reference clock signal using a first PLL stage with a high-Q voltage-controlled oscillator (VCO). This first PLL stage has a low loop bandwidth, and thus acts as a low-pass filter (LPF) to remove the reference clock jitter. The low jitter intermediate clock signal is distributed to one or more second PLL stages that derive higher frequency transmit and/or receive clock signals from the intermediate clock signal. Each second PLL stage includes a low-Q VCO that exhibits a considerable tuning range to support a number of transmit and receive data rates.

Abstract: Margin-testing circuits and methods rely upon the statistics of sampled data to explore the margin characteristics of received data. One margining circuit samples an incoming data stream N times at each of many sample points, each sample point representing a unique sample voltage, unique sample timing, or a unique combination of sample voltage and sample timing. The number of ones sampled at a particular point is a measure of the ones probability for that sample point. The ones probabilities for the collection of unique sample points are then analyzed to measure various aspects of the received data stream, including the data margin.

Abstract: A differential amplifier and method of using same are disclosed. In one particular exemplary embodiment, the present invention may be realized as a circuit comprising a differential amplifier for receiving a differential input signal and generating a differential output signal, a comparator for generating an adjustment signal based at least in part upon the differential output signal, and a current controller for controlling current steering and at least one offset current in the differential amplifier based at least in part upon the adjustment signal and a current steering control signal.

Abstract: An integrated circuit receives a request to adjust the phase of an output clock being generated by a phase-locked loop based on an input reference clock. A digital or analog offset value is injected into the phase-locked loop based on a phase adjustment amount contained in the phase adjustment request. Alternatively, a programmable delay is implemented in the PLL feedback path or the reference clock path. The delay is based on the phase adjustment request.

Abstract: A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

Abstract: A receive circuit having a sampling circuit and a threshold generating circuit. The sampling circuit generates a first sample value having either a first state or a second state according whether an incoming signal exceeds a first threshold level, the first threshold level corresponding to a first threshold value. The threshold generating circuit combines a first control value and a second control value to generate the first threshold value and provides the first threshold value to the sampling circuit.

Abstract: An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.