Abstract: A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an upper LSB sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal. The differential multi-PAM extractor circuit also comprises a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal.

Abstract: A phase-locked loop receives multiple input clocks, one of which is selected for use by the PLL at any one time. The phase difference(s) between non-selected input clocks and a feedback signal of the PLL, is monitored and stored. When a switch occurs to using a non-selected clock as the input clock of the PLL, the stored phase difference, typically a DC offset value, is injected into the phase-locked loop to compensate for the phase difference between the clocks.

Abstract: A bus driver circuit having slew rate control. According to one embodiment, the bus driver circuit includes the following elements: a first circuit having an input configured to receive a data signal and an output operative to output a drive signal in response to the data signal; a second circuit coupled in parallel with the first circuit and operative to receive a slew rate control signal; and a slew rate indicator circuit coupled to the second circuit. The slew rate indicator circuit determines the state of the slew rate control signal in response to operating conditions that cause variations in the slew rate of the drive signal such that when the slew rate control signal is asserted, the second circuit is enabled to affect the slew rate of the drive signal. For one embodiment, the slew rate indicator includes a pulse generator circuit and a clocked comparator circuit.