Patents by Inventor Bruno W. Garlepp
Bruno W. Garlepp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8634452Abstract: An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.Type: GrantFiled: June 7, 2012Date of Patent: January 21, 2014Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, Jr., Carl W. Werner
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Patent number: 8630317Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: GrantFiled: April 13, 2012Date of Patent: January 14, 2014Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Patent number: 8559493Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.Type: GrantFiled: October 26, 2009Date of Patent: October 15, 2013Assignee: Rambus Inc.Inventors: Andrew Ho, Vladimir Stojanovic, Bruno W. Garlepp, Fred F. Chen
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Patent number: 8428196Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.Type: GrantFiled: May 11, 2012Date of Patent: April 23, 2013Assignee: Rambus Inc.Inventors: Vladimir M. Stojanovic, Mark A. Horowitz, Jared L. Zerbe, Anthony Bessios, Andrew C. C. Ho, Jason C. Wei, Grace Tsang, Bruno W. Garlepp
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Patent number: 8385492Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.Type: GrantFiled: February 14, 2012Date of Patent: February 26, 2013Assignee: Rambus Inc.Inventors: Andrew Ho, Vladimir Stojanovic, Bruno W. Garlepp, Fred F. Chen
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Publication number: 20130010855Abstract: An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.Type: ApplicationFiled: June 7, 2012Publication date: January 10, 2013Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, JR., Carl W. Werner
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Publication number: 20120224621Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.Type: ApplicationFiled: May 11, 2012Publication date: September 6, 2012Inventors: Vladimir M. Stojanovic, Mark A. Horowitz, Jared L. Zerbe, Anthony Bessios, Andrew C.C. Ho, Jason C. Wei, Grace Tsang, Bruno W. Garlepp
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Publication number: 20120213267Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.Type: ApplicationFiled: April 30, 2012Publication date: August 23, 2012Inventors: Vladimir M. Stojanovic, Mark A. Horowitz, Jared L. Zerbe, Anthony Bessios, Andrew C.C. Ho, Jason C. Wei, Grace Tsang, Bruno W. Garlepp
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Publication number: 20120204054Abstract: An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.Type: ApplicationFiled: April 13, 2012Publication date: August 9, 2012Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Publication number: 20120189045Abstract: A data receiver circuit includes an interface to receive an input signal that includes a data signal and a clock signal superimposed on the data signal. The data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate. The clock signal has a frequency N times the associated symbol rate, where N is an integer. A phase-locked loop (PLL) coupled to the interface extracts the clock signal from the input signal to provide an extracted clock signal. A phase interpolator adjusts the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal. A sampling circuit samples the data signal at a sampling point. The sampling circuit is synchronized to the phase-adjusted extracted clock signal.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Inventors: Aliazam Abbasfar, Amir Amirkhany, Bruno W. Garlepp
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Patent number: 8199859Abstract: An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.Type: GrantFiled: October 4, 2010Date of Patent: June 12, 2012Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, Jr., Carl W. Werner
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Publication number: 20120140812Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.Type: ApplicationFiled: February 14, 2012Publication date: June 7, 2012Applicant: Rambus Inc.Inventors: Andrew Ho, Vladimir Stojanovic, Bruno W. Garlepp, Fred F. Chen
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Patent number: 8170067Abstract: A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.Type: GrantFiled: April 27, 2009Date of Patent: May 1, 2012Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu, Roxanne Vu, Jun Kim, Bruno W. Garlepp, Tsyr-Chyang Ho, Benedict Chung-Kwong Lau
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Patent number: 8170163Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.Type: GrantFiled: February 23, 2010Date of Patent: May 1, 2012Assignee: Rambus Inc.Inventors: Vladimir M. Stojanovic, Mark A. Horowitz, Jared L. Zerbe, Anthony Bessios, Andrew C. C. Ho, Jason C. Wei, Grace Tsang, Bruno W. Garlepp
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Patent number: 8149972Abstract: A data receiver circuit includes an interface to receive an input signal that includes a data signal and a clock signal superimposed on the data signal. The data signal has an associated symbol rate and an associated symbol period equal to the reciprocal of the associated symbol rate. The clock signal has a frequency N times the associated symbol rate, where N is an integer. A phase-locked loop (PLL) coupled to the interface extracts the clock signal from the input signal to provide an extracted clock signal. A phase interpolator adjusts the phase of the extracted clock signal to provide a phase-adjusted extracted clock signal. A sampling circuit samples the data signal at a sampling point. The sampling circuit is synchronized to the phase-adjusted extracted clock signal.Type: GrantFiled: May 28, 2008Date of Patent: April 3, 2012Assignee: Rambus Inc.Inventors: Aliazam Abbasfar, Amir Amirkhany, Bruno W. Garlepp
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Publication number: 20110140741Abstract: A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.Type: ApplicationFiled: October 4, 2010Publication date: June 16, 2011Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, JR., Carl W. Werner
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Patent number: 7809088Abstract: A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.Type: GrantFiled: November 23, 2009Date of Patent: October 5, 2010Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, Jr., Carl W. Werner
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Publication number: 20100142610Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.Type: ApplicationFiled: February 23, 2010Publication date: June 10, 2010Inventors: Vladimir M. Stojanovic, Mark A. Horowitz, Jared L. Zerbe, Anthony Bessios, Andrew C.C. Ho, Jason C. Wei, Grace Tsang, Bruno W. Garlepp
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Publication number: 20100134153Abstract: A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and sample data of the input signal on a second phase of the clock. The multiphase receiver also includes an equalization circuit to adjust integration by the first integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the first integrating receiver, and to adjust integration by the second integrating receiver dependent on a result of integration of data previously received by an integrating receiver distinct from the second integrating receiver.Type: ApplicationFiled: November 23, 2009Publication date: June 3, 2010Inventors: Jared L. Zerbe, Bruno W. Garlepp, Pak S. Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos, Billy W. Garrett, JR., Carl W. Werner
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Patent number: 7715501Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.Type: GrantFiled: October 18, 2004Date of Patent: May 11, 2010Assignee: Rambus, Inc.Inventors: Vladimir M. Stojanovic, Mark A. Horowitz, Jared L. Zerbe, Anthony Bessios, Andrew C. C. Ho, Jason C. Wei, Grace Tsang, Bruno W. Garlepp