Abstract: A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.

Abstract: A differential amplifier and method of using same are disclosed. In one particular exemplary embodiment, the present invention may be realized as a circuit comprising a differential amplifier for receiving a differential input signal and generating a differential output signal, a comparator for generating an adjustment signal based at least in part upon the differential output signal, and a current controller for controlling current steering and at least one offset current in the differential amplifier based at least in part upon the adjustment signal and a current steering variable signal.

Abstract: A first phase-locked loop circuit that includes a crystal oscillator, receives a reference clock signal and supplies a first phase-locked loop output signal based on the reference clock during normal operational mode and a stored value in holdover mode. A second phase-locked loop circuit receives the first phase-locked loop output signal and utilizes the first phase-locked loop output signal when generating an output clock in holdover mode. The second phase-locked loop utilizes the first phase-locked loop output signal during operation in the holdover mode to generate the output clock and utilizes the reference clock during normal operational mode to generate the output clock. Alternatively, the second phase-locked loop utilizes the first phase-locked loop output signal both during operation in the holdover mode and during normal operational mode to generate the output clock.

Abstract: A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

Abstract: An integrated circuit device includes one or more calibration paths including one or more devices. A signal generator is coupled to at least one calibration path and configured to provide the calibration path with a calibration signal having known characteristics. A controller is coupled to the signal generator and the calibration path and configured to adjust the signal generator and at least one parameter associated with at least one device in the calibration path.

Abstract: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM sigsnals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

Abstract: An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

Abstract: A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.

Abstract: An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

Abstract: An integrated circuit memory device that include an input receiver, an output driver, and a capacitive coupling element. The capacitive coupling element includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is coupled to the input receiver and the output driver, an the second capacitor electrode couples to an external signal line. Delay modulated data is received by the input receiver from the external signal line via the capacitive coupling element.

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

Abstract: An exemplary PLL circuit includes a VCO responsive to a plurality of sub-varactor control signals. A digital loop filter for the PLL digitally generates a varactor control word, which is digitally expanded into a plurality of digital values, each of which is conveyed to a corresponding one of a plurality of DACs. A multiplexer is configured to respectively convey the DAC output signals to a group of sub-varactor control signals according to the varactor control word, and to drive remaining sub-varactor control signals to either the full-scale high value or the full-scale low value of the DAC outputs. Each of the DACs preferably includes a hybrid first order/second order sigma-delta modulator, and in certain embodiments, a NRZ-to-RZ coder circuit, and a linear filter circuit.

Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract: A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.

Abstract: An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

Abstract: A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Abstract: A bus system for use with addressable memory has a global bus of uni-directional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus. First and second global bus terminators are coupled to the first and second ends of the global bus, respectively. One or more subsystems are connected in parallel to each other and to the master device via the global bus. Each subsystem includes a local bus, one or more slave devices coupled to the local bus, a write buffer that receives incoming signals from the master device via the global bus and transmits the incoming signals to the one or more slave devices via the local bus, and a read buffer that receives outgoing signals from the one or more slave devices via the local bus and transmits the outgoing signals to the master device via the global bus.

Abstract: A bus system comprising a master connected to one or more slave devices via a bus is disclosed. The bus system is able to effectively communicate control information during a calibration phase and to individually determine appropriate timing and/or voltage offsets for each slave device. The offsets are used to optimize transfer timing (including duty cycle characteristics), signal equalization, and voltage levels for data exchanged between the master and the slave devices.