Abstract: An energy storage device includes a first electrode (110, 510) including a first plurality of channels (111, 512) that contain a first electrolyte (150, 514) and a second electrode (120, 520) including a second plurality of channels (121, 522) that contain a second electrolyte (524). The first electrode has a first surface (115, 511) and the second electrode has a second surface (125, 521). At least one of the first and second electrodes is a porous silicon electrode, and at least one of the first and second surfaces comprises a passivating layer (535).

Abstract: Hybrid electrochemical capacitors, electronic devices using such capacitors, and associated methods are disclosed. In an example, a hybrid electrochemical capacitor can include a first electrode made from Mg, Na, Zn, Al, Sn, or Li, a second electrode made from a porous material such as porous carbon or passivated porous silicon, and an electrolyte. The hybrid electrochemical capacitors can have enhanced voltage and energy density compared to other electrochemical capacitors, and enhanced power density compared to batteries.

Abstract: Ultrafast battery devices having enhanced reliability and power density are provided. Such batteries can include a cathode including a first silicon substrate having a cathode structured surface, an anode including a second silicon substrate having an anode structured surface positioned adjacent to the cathode such that the cathode structured surface faces the anode structured surface, and an electrolyte disposed between the cathode and the anode. The anode structured surface can be coated with an anodic active material and the cathode structured surface can be coated with a cathodic active material.

Abstract: Ultracapacitor electrodes having an enhanced electrolyte-accessible surface area are provided. Such electrodes can include a porous substrate having a solution side and a collector side, the collector side operable to couple to a current collector and the solution side positioned to interact with an electrolytic solution when in use. The electrode can also include a conductive coating formed on the solution side of the porous substrate. The coating can have a first side positioned to interact with an electrolytic solution when in use and a second side opposite the first side. The coating can have discontinuous regions that allow access of an electrolyte solution to the second side during use to enhance electrolyte-accessible surface area of the conductive coating.

Abstract: Amorphous silicon anode electrodes and devices for a rechargeable batteries having enhanced structural stabilities are provided. An amorphous silicon anode can include an electrically conductive substrate and an electrode layer deposited onto the substrate, where the electrode layer is comprised of one or more amorphous silicon structures, and the amorphous silicon structures have at least one dimension that is less than or equal to about 500 nm.

Abstract: An energy storage device includes an electrode made from an active material in which a plurality of channels have been etched. The channels are coated with an electrically functional substance selected from a conductor and an electrolyte.

Abstract: Electrodes, energy storage devices using such electrodes, and associated methods are disclosed. In an example, an electrode for use in an energy storage device can comprise porous disks comprising a porous material, the porous disks having a plurality of channels and a surface, the plurality of channels opening to the surface; and a structural material encapsulating the porous disks; where the structural material provides structural stability to the electrode during use.

Abstract: In one embodiment, a structure for an energy storage device may include a first nanostructured substrate having a conductive layer and a dielectric layer formed on the conductive layer. A second nanostructured substrate includes another conductive layer. A separator separates the first and second nanostructured substrates and allows ions of an electrolyte to pass through the separator. The structure may be a nanostructured electrolytic capacitor with the first nanostructured substrate forming a positive electrode and the second nanostructured substrate forming a negative electrode of the capacitor.

Abstract: An energy storage device includes a first electrode (110, 510) including a first plurality of channels (111, 512) that contain a first electrolyte (150, 514) and a second electrode (120, 520) including a second plurality of channels (121, 522) that contain a second electrolyte (524). The first electrode has a first surface (115, 511) and the second electrode has a second surface (125, 521). At least one of the first and second electrodes is a porous silicon electrode, and at least one of the first and second surfaces comprises a passivating layer (535).

Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Abstract: An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.

Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming a barrier layer. The method of forming the barrier layer includes providing a workpiece, forming a first material layer over the workpiece, the first material layer comprising a nitride-based metal compound. A second material layer is formed over the first material layer. The second material layer comprises Ta or Ti. The barrier layer comprises the first material layer and at least the second material layer.

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes.

Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Abstract: A semiconductor device includes a material layer and a first barrier layer disposed over the material layer. The first barrier layer includes a nitrogen-rich region formed at a top surface of the first barrier layer. A conductor is disposed over the first barrier layer such that the first barrier layer and the nitrogen-rich region form a barrier layer between the material layer and the conductor.