Patents by Inventor Byeongju Park
Byeongju Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7323761Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.Type: GrantFiled: November 12, 2004Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Byeongju Park, Subramanian S. Iyer, Chandrasekheran Kothandaraman
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Publication number: 20070284693Abstract: An electrically programmable fuse is provided which includes a cathode, an anode, and a fuse link conductively connecting the cathode to the anode. The cathode, the anode and the fuse link each have a length in a direction of current between the anode and cathode. Each of the cathode, the anode and the fuse link also has a width in a direction transverse to the respective length. At a cathode junction where the cathode meets the fuse link, the width of the fuse link decreases substantially and abruptly relative to the width of the cathode. The width of the fuse link increases only gradually in a direction towards an anode junction where the fuse link meets the anode.Type: ApplicationFiled: June 9, 2006Publication date: December 13, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deok-Kee Kim, Byeongju Park
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Publication number: 20070195629Abstract: A system and method for achieving enhanced e-fuse programming reliability. By providing an e-fuse device with redundantly coded fuse structures each with a differing fuse size dimension, reliable encoding of a fuse with a programmed bit is enhanced. That is, for each e-fuse device, each of the multiple fuse structures and a corresponding programming devices associated with each fuse structure is dimensioned to achieve the coding redundancy such that one fuse structure of the multiple fuse structures provides for a current flow of sufficient current density to ensure programming reliability of the e-fuse device. In one embodiment, each the corresponding programming transistor device is of substantially identical size and, each fuse structure of the multiple fuse structures is of a different size. Alternately, each fuse structure is of substantially identical size and each programming transistor device is of a different size, thereby ensuring reliable coding over a programmed current range.Type: ApplicationFiled: February 22, 2006Publication date: August 23, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Byeongju Park, John Safran
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Patent number: 7254078Abstract: A system and method for achieving enhanced e-fuse programming reliability. By providing an e-fuse device with redundantly coded fuse structures each with a differing fuse size dimension, reliable encoding of a fuse with a programmed bit is enhanced. That is, for each e-fuse device, each of the multiple fuse structures and a corresponding programming devices associated with each fuse structure is dimensioned to achieve the coding redundancy such that one fuse structure of the multiple fuse structures provides for a current flow of sufficient current density to ensure programming reliability of the e-fuse device. In one embodiment, each the corresponding programming transistor device is of substantially identical size and, each fuse structure of the multiple fuse structures is of a different size. Alternately, each fuse structure is of substantially identical size and each programming transistor device is of a different size, thereby ensuring reliable coding over a programmed current range.Type: GrantFiled: February 22, 2006Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Byeongju Park, John M. Safran
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Patent number: 7227207Abstract: The present invention provides a dense semiconductor fuse array having common cathodes. The dense semiconductor fuse array of the present invention occupies less area than conventional semiconductor fuse arrays, can comprise integrated diodic components, and can require only one metal wiring layer for making electrical connections to the fuse array.Type: GrantFiled: March 3, 2005Date of Patent: June 5, 2007Assignee: International Business Machines CorporationInventors: Byeongju Park, Chandrasekharan Kothandaraman, Subramanian S. Iyer
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Publication number: 20060197179Abstract: The present invention provides a dense semiconductor fuse array having common cathodes. The dense semiconductor fuse array of the present invention occupies less area than conventional semiconductor fuse arrays, can comprise integrated diodic components, and can require only one metal wiring layer for making electrical connections to the fuse array.Type: ApplicationFiled: March 3, 2005Publication date: September 7, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Byeongju Park, Chandrasekharan Kothandaraman, Subramanian Iyer
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Patent number: 7081387Abstract: A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.Type: GrantFiled: August 16, 2004Date of Patent: July 25, 2006Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Jack A. Mandelman, Byeongju Park
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Publication number: 20050095831Abstract: Under the present invention, a layer of amorphous silicon is formed over a layer of gate dielectric. Over the layer of amorphous silicon, a gate cap dielectric is formed. The layer of amorphous silicon is then confined by at least one spacer, which is deposited under a low temperature process. Once the at least one spacer is in place, the amorphous silicon is exposed to a temperature sufficiently high to convert the amorphous silicon to polysilicon.Type: ApplicationFiled: November 4, 2003Publication date: May 5, 2005Applicant: International Business Machines CorporationInventors: Karanam Balasubramanyam, Serge Biesemans, Byeongju Park
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Patent number: 6884672Abstract: Under the present invention, a layer of amorphous silicon is formed over a layer of gate dielectric. Over the layer of amorphous silicon, a gate cap dielectric is formed. The layer of amorphous silicon is then confined by at least one spacer, which is deposited under a low temperature process. Once the at least one spacer is in place, the amorphous silicon is exposed to a temperature sufficiently high to convert the amorphous silicon to polysilicon. By waiting until the amorphous silicon is confined within the at least one spacer before converting it to polysilicon, the variation in gate length is reduced.Type: GrantFiled: November 4, 2003Date of Patent: April 26, 2005Assignee: International Business Machines CorporationInventors: Karanam Balasubramanyam, Serge Biesemans, Byeongju Park
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Publication number: 20050012145Abstract: A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.Type: ApplicationFiled: August 16, 2004Publication date: January 20, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Jack Mandelman, Byeongju Park
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Patent number: 6818952Abstract: A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.Type: GrantFiled: October 1, 2002Date of Patent: November 16, 2004Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Jack A. Mandelman, Byeongju Park
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Patent number: 6780735Abstract: We provide a method of doping an Si or SiGe film with carbon or boron. By reducing the silicon precursor pressure, heavily-doped films may be obtained. A single dopant source may be used. The doped Si and SiGe films are of suitable quality for use in a transistor such as an HBT.Type: GrantFiled: April 30, 2001Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: Basanth Jagannathan, Jack O. Chu, Ryan W. Wuthrich, Byeongju Park
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Publication number: 20040061172Abstract: A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.Type: ApplicationFiled: October 1, 2002Publication date: April 1, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Jack A. Mandelman, Byeongju Park
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Patent number: 6635543Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.Type: GrantFiled: December 31, 2002Date of Patent: October 21, 2003Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Jack A. Mandelman, Dan Moy, Byeongju Park, William R. Tonti
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Publication number: 20030104658Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.Type: ApplicationFiled: December 31, 2002Publication date: June 5, 2003Inventors: Toshiharu Furukawa, Jack A. Mandelman, Dan Moy, Byeongju Park, William R. Tonti
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Patent number: 6555891Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.Type: GrantFiled: October 17, 2000Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Jack A. Mandelman, Dan Moy, Byeongju Park, William R. Tonti
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Patent number: 6509611Abstract: A wrapped-gate transistor includes a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer is formed on the substrate. A gate electrode is formed on the gate dielectric layer to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric therebetween. The substrate is a silicon island formed on an insulation layer of an SOI (silicon-on-insulator) substrate or on a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces.Type: GrantFiled: September 21, 2001Date of Patent: January 21, 2003Assignee: International Business Machines CorporationInventors: Byeongju Park, Toshiharu Furukawa, Jack A. Mandelman
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Patent number: 6488778Abstract: An apparatus and method for controlling wafer temperature and environment is provided. The apparatus includes a batch processing fixture for batch processing wafers at a first elevated temperature. The batch of wafers is not substantially ramped in temperature within the batch processing fixture. The apparatus also includes a single wafer processing apparatus for rapidly ramping temperature of a wafer of the batch from the first elevated temperature wherein a uniform temperature across the wafer is maintained during the ramping. Another embodiment of the apparatus (10) includes an RTP chamber (20) having an inert or reducing environment and that includes a pedestal (24) for holding a single wafer (16) and a heater unit (22) arranged so as to uniformly and rapidly heat the single wafer.Type: GrantFiled: March 16, 2000Date of Patent: December 3, 2002Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Peter A. Emmi, Walter J. Frey, Michael J. Gambero, Neena Garg, Byeongju Park, Donald L. Wilson
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Publication number: 20020160587Abstract: We provide a method of doping an Si or SiGe film with carbon or boron. By reducing the silicon precursor pressure, heavily-doped films may be obtained. A single dopant source may be used. The doped Si and SiGe films are of suitable quality for use in a transistor such as an HBT.Type: ApplicationFiled: April 30, 2001Publication date: October 31, 2002Inventors: Basanth Jagannathan, Jack O. Chu, Ryan W. Wuthrich, Byeongju Park
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Publication number: 20020106857Abstract: A method and structure for a fabricating roughened surface walls of a capacitor, such as a deep trench capacitor. The invention starts with a silicon surface and forms silicon germanium grains on the silicon surface. A portion of the silicon surface remains exposed and is etched selective to the silicon germanium grains. The silicon germanium grains are then removed from the silicon surface. The silicon surface is doped after the silicon germanium grains are removed.Type: ApplicationFiled: February 6, 2001Publication date: August 8, 2002Applicant: International Business Machines CorporationInventors: Rajarao Jammy, Irene McStay, Byeongju Park, Ravikumar Ramachandran, Joseph F. Shepard, Helmut Tews