Abstract: A disclosed process use low pressure chemical vapor deposition (LPCVD) of doped oxide film on a substrate. The process includes the steps of providing a substrate in an LPCVD reactor and flowing BTBAS and oxygen into the LPCVD reactor to react on the substrate to deposit an oxide film on the substrate. A doped precursor is flowed into the LPCVD reactor to dope the oxide film as it is deposited on the substrate. This process produces doped oxide film at a relatively low LPCVD reaction temperature.

Abstract: A method fabricates a bottle shaped trench by providing a substrate with a substantially vertical trench therein and a collar about an upper interior portion of the trench and isotropically HCl etching a lower interior portion of the trench under the collar for expansion thereof, wherein the expanded lower interior portion has a wider cross section than that of the upper interior portion of the trench. Further, the method performs potential in-situ process integration with a gas phase doping in the same tool as the one that performed the gas phase etching process.

Abstract: A trench capacitor comprising a substrate, a trench formed in the substrate, and conductive doped germanium or silicon-germanium alloy fill material completely filling the trench. The process for creating the capacitor comprises depositing the conductive doped germanium or silicon-germanium alloy in the trench and in a fill layer over the substrate and annealing the wafer at a temperature at which the fill layer melts and completely flows into the trench but the wafer does not melt. The process further includes depositing a silicon cap layer on top of the fill layer to prevent oxidation of the fill layer. The trench may further include one or more of a buffer layer, a metal layer, and a thermal-stress-reduction layer between the trench walls and the fill material.

Abstract: A dynamic random-access memory (DRAM) cell comprising a trench capacitor and an access transistor and a process of manufacturing the cell. The trench capacitor is formed in a trench and is positioned at the bottom of the trench. The access transistor has an active area formed in the trench adjacent the trench capacitor and adjacent the top surface of the substrate. The active area provides an electrical connection with the trench capacitor. The DRAM cell design reclaims the active area above the trench capacitor.

Abstract: A vertical channel field effect transistor and a process of manufacturing the same. The vertical channel field effect transistor is disposed on a surface of a substrate and comprises an epitaxial silicon stack having a bottom terminal comprising heavily doped silicon, a channel comprising lightly doped silicon of opposite doping type from the bottom terminal, and a top terminal comprising heavily doped silicon of the same doping type as the bottom terminal. The vertical channel field effect transistor also comprises a gate dielectric layer covering at least a portion of the bottom terminal, the channel, and the top terminal, and a gate in contact with the gate dielectric layer. The gate is positioned adjacent the channel and adjacent at least a portion of the bottom terminal and top terminal. The channel has a thickness between the bottom terminal and the top terminal from about 50 angstroms to about 800 angstroms.

Abstract: A semiconductor structure of reduced contact resistance is provided by providing a layer of amorphous silicon-derived material on an epitaxial silicon substrate having an average dopant concentration of at least about 1020 atoms/cm3 in the contact material within about 500 Å of the substrate.

Abstract: A trench capacitor comprising a substrate, a trench formed in the substrate, and conductive doped germanium or silicon-germanium alloy fill material completely filling the trench. The process for creating the capacitor comprises depositing the conductive doped germanium or silicon-germanium alloy in the trench and in a fill layer over the substrate and annealing the wafer at a temperature at which the fill layer melts and completely flows into the trench but the wafer does not melt. The process further includes depositing a silicon cap layer on top of the fill layer to prevent oxidation of the fill layer. The trench may further include one or more of a buffer layer, a metal layer, and a thermal-stress-reduction layer between the trench walls and the fill material.

Abstract: A pass-through, wafer-processing tool for treating a moving semiconductor wafer with a process gas. The tool comprises an open-ended, non-isolated processing module having a wafer path through the module, vacuum manifolds mounted adjacent the wafer entry to and wafer exit from the module, and a gas manifold between the vacuum manifolds adapted to direct process gas onto the moving wafer. The gas manifold may deliver plasma ions generated by a remote plasma unit outside the module. Instead, a plasma may be generated inside the pass-through, wafer processing tool and, if so, the tool further comprises a top electrode mounted above the wafer passage. A wafer handler, which may be a robotic handler, carries the wafer through the wafer passage and serves as a bottom electrode.

Abstract: A trench capacitor structure suitable for use in a semiconductor integrated circuit device and the process sequence used to form the structure. The trench capacitor provides increased capacitance by including a capacitor plate consisting of textured, hemispherical-grained silicon. The trench capacitor also includes a buried plate to reduce depletion of stored charge from the capacitor.