Patents by Inventor Carl Ramey
Carl Ramey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11093215Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.Type: GrantFiled: November 20, 2020Date of Patent: August 17, 2021Assignee: Lightmatter, Inc.Inventors: Nicholas C. Harris, Darius Bunandar, Michael Gould, Carl Ramey, Shashank Gupta, Carlos Dorta-Quinones
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Publication number: 20210242124Abstract: Described herein are photonic communication platforms and related packages. In one example, a photonic package includes a substrate carrier having a recess formed through the top surface of the substrate carrier. The substrate carrier may be made of a ceramic laminate. A photonic substrate including a plurality of photonic modules is disposed in the recess. The photonic modules may be patterned using a common photomask, and as a result, may share a same layer pattern. A plurality of electronic dies may be positioned on top of respective photonic modules. The photonic modules enable communication among the dies in the optical domain. Power delivery substrates may be used to convey electric power from the substrate carrier to the electronic dies and to the photonic substrate. Power delivery substrates may be implemented, for example, using bridge dies or interposers (e.g., silicon or organic interposers).Type: ApplicationFiled: February 2, 2021Publication date: August 5, 2021Applicant: Lightmatter, Inc.Inventors: Sukeshwar Kannan, Carl Ramey, Jon Elmhurst, Darius Bunandar, Nicholas C. Harris
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Publication number: 20210224454Abstract: Aspects relate to a photonic processing system, an integrated circuit, and a method of operating an integrated circuit to control components to modulate optical signals. A photonic processing system, comprising: a photonic integrated circuit comprising: a first electrically-controllable photonic component electrically coupling an input pin to a first output pin; and a second electrically-controllable photonic component electrically coupling the input pin to a second output pin.Type: ApplicationFiled: January 14, 2021Publication date: July 22, 2021Applicant: Lightmatter, Inc.Inventors: Carl Ramey, Darius Bunandar, Nicholas C. Harris
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Patent number: 11036002Abstract: Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.Type: GrantFiled: March 5, 2020Date of Patent: June 15, 2021Assignee: Lightmatter, Inc.Inventors: Nicholas C. Harris, Carl Ramey, Michael Gould, Thomas Graham, Darius Bunandar, Ryan Braid, Mykhailo Tymchenko
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Publication number: 20210157878Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.Type: ApplicationFiled: November 23, 2020Publication date: May 27, 2021Applicant: Lightmatter, Inc.Inventors: Darius Bunandar, Nicholas C. Harris, Michael Gould, Carl Ramey, Shashank Gupta, Carlos Dorta-Quinones
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Publication number: 20210157547Abstract: Photonic processors are described. The photonic processors described herein are configured to perform matrix-matrix (e.g., matrix-vector) multiplication. Some embodiments relate to photonic processors arranged according to a dual-rail architecture, in which numeric values are encoded in the difference between a pair optical signals (e.g., in the difference between the powers of the optical signals). Relative to other architectures, these photonic processors exhibit increased immunity to noise. Some embodiments relate to photonic processors including modulatable detector-based multipliers. Modulatable detectors are detectors designed so that the photocurrent can be modulated according to an electrical control signal. Photonic processors designed using modulatable detector-based multipliers are significantly more compact than other types of photonic processors.Type: ApplicationFiled: November 20, 2020Publication date: May 27, 2021Applicant: Lightmatter, Inc.Inventors: Darius Bunandar, Nicholas C. Harris, Michael Gould, Carl Ramey, Shashank Gupta, Carlos Dorta-Quinones
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Publication number: 20210118853Abstract: A memory device is described. The memory device comprises a plurality of stacked memory layers, wherein each of the plurality of stacked memory layers comprises a plurality of memory cells. The memory device further comprises an optical die bonded to the plurality of stacked memory layers and in electrical communication with the stacked memory layers through one or more interconnects. The optical die comprises an optical transceiver, and a memory controller configured to control read and/or write operations of the stacked memory layers. The optical die may be positioned at one end of the plurality of stacked memory layers. The one or more interconnects may comprise one or more through silicon vias (TSV). The plurality of memory cells may comprise a plurality of solid state memory cells. The memory devices described herein can enable all-to-all, point-to-multipoint and ring architectures for connecting logic units with memory devices.Type: ApplicationFiled: April 30, 2019Publication date: April 22, 2021Applicant: Lighmatter, Inc.Inventors: Nicholas C. Harris, Carl Ramey
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Patent number: 10942876Abstract: One embodiment includes a computing device including peripheral component bus interfaces for connection to a peripheral component bus, a first integrated circuit (IC) chip comprising a processor to initiate a register setup process of the device, a second IC chip including a tile processor including multiple tiles, each tile including at least a processing core configured to generate requests to at least one of the peripheral component bus interfaces, steering configuration registers to store steering configuration data, and steering logic to steer the generated requests responsively to the steering configuration data in the steering configuration registers, and steering register setup circuitry including a multicaster and a register setup memory, wherein the processor is configured to write the steering configuration data to the register setup memory, and the multicaster is configured to multicast the steering configuration data written to the register setup memory to the steering configuration registers ofType: GrantFiled: November 14, 2019Date of Patent: March 9, 2021Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Carl Ramey, Christopher Jackson, Diane Orf, Matt Orsini, Michael Cotsford, Mark B. Rosenbluth, Rui Xu
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Publication number: 20210036783Abstract: Systems and methods for performing signed matrix operations using a linear photonic processor are provided. The linear photonic processor is formed as an array of first amplitude modulators and second amplitude modulators, the first amplitude modulators configured to encode elements of a vector into first optical signals and the second amplitude modulators configured to encode a product between the vector elements and matrix elements into second optical signals. An apparatus may be used to implement a signed value of an output of the linear processor. The linear photonic processor may be configured to perform matrix-vector and/or matrix-matrix operations.Type: ApplicationFiled: July 28, 2020Publication date: February 4, 2021Applicant: Lightmatter, Inc.Inventors: Darius Bunandar, Nicholas C. Harris, Michael Gould, Carl Ramey, Tomo Lazovich
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Publication number: 20210003904Abstract: Methods and apparatus for tuning a photonics-based component. An opto-electrical detector is configured to output an electrical signal based on a measurement of light intensity of the photonics-based component, the light intensity being proportional to an amount of detuning of the photonics-based component. Analog-to-digital conversion (ADC) circuitry is configured to output a digital signal based on the electrical signal output from the opto-electrical detector. Feedback control circuitry is configured to tune the photonics-based component based, at least in part, on the digital signal output from the ADC circuitry.Type: ApplicationFiled: July 1, 2020Publication date: January 7, 2021Applicant: Lightmatter, Inc.Inventors: Carlos Dorta-Quinones, Carl Ramey, Omer Ozgur Yildirim, Chithira Ravi, Shashank Gupta, Nicholas C. Horris
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Patent number: 10877761Abstract: A multiprocessor device includes cores and at least one ingress-write ordering circuitry (IWOC) including first and second counters associated with first and second destinations. The IWOC is configured to assign sequential numbers to write transactions received from a source, according to an order of reception at the IWOC, and to forward the write transactions from the IWOC to the first and second write-transaction destinations, while preserving the order, by incrementing the first and second counters such that both the first counter and the second counter track a sequential number of a next write transaction that the IWOC will forward, forwarding a first write transaction to the first destination only provided that the sequential number of the first write transaction matches the first counter, and forwarding a second write transaction to the second destination only provided that the sequential number of the second write transaction matches the second counter.Type: GrantFiled: December 8, 2019Date of Patent: December 29, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Rui Xu, Carl Ramey, Benjamin Cahill, Diane Orf, Mark B. Rosenbluth, Michael Cotsford
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Publication number: 20200396007Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.Type: ApplicationFiled: August 6, 2020Publication date: December 17, 2020Applicant: Lightmatter, Inc.Inventors: Darius Bunandar, Nicholas C. Harris, Carl Ramey
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Publication number: 20200284981Abstract: Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.Type: ApplicationFiled: March 5, 2020Publication date: September 10, 2020Applicant: Lightmatter, Inc.Inventors: Nicholas C. Harris, Carl Ramey, Michael Gould, Thomas Graham, Darius Bunandar, Ryan Braid, Mykhailo Tymchenko
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Patent number: 10763974Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.Type: GrantFiled: May 14, 2019Date of Patent: September 1, 2020Assignee: Lightmatter, Inc.Inventors: Darius Bunandar, Nicholas C. Harris, Carl Ramey
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Publication number: 20200116930Abstract: Photonic packages are described. One such photonic package includes a photonic chip, an application specific integrated circuit, and optionally, an interposer. The photonic chip includes photonic microelectromechanical system (MEMS) devices. A photonic package may include a material layer patterned to include recesses. The recesses are aligned with the photonic MEMS devices so as to form enclosed cavities around the photonic MEMS devices. This arrangement preserves the integrity of the photonic MEMS devices.Type: ApplicationFiled: October 15, 2019Publication date: April 16, 2020Applicant: Lightmatter, Inc.Inventors: Sukeshwar Kannan, Carl Ramey, Michael Gould, Nicholas C. Harris
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Publication number: 20190356394Abstract: Aspects relate to a photonic processing system, a photonic processor, and a method of performing matrix-vector multiplication. An optical encoder may encode an input vector into a first plurality of optical signals. A photonic processor may receive the first plurality of optical signals; perform a plurality of operations on the first plurality of optical signals, the plurality of operations implementing a matrix multiplication of the input vector by a matrix; and output a second plurality of optical signals representing an output vector. An optical receiver may detect the second plurality of optical signals and output an electrical digital representation of the output vector.Type: ApplicationFiled: May 14, 2019Publication date: November 21, 2019Inventors: Darius Bunandar, Nicholas C. Harris, Carl Ramey
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Patent number: 10148258Abstract: An integrated circuit and method are described for compensating for voltage droop on an integrated circuit using a power supply voltage monitoring circuit and a high-resolution adaptive clock stretching circuit. In some example embodiments, the method includes monitoring power supply voltage on an integrated circuit, detecting a voltage droop such as a dynamic loss of power supply in the integrated circuit, and stretching a current clock cycle, according to the detected voltage droop, to provide more time for logic on the integrated circuit to complete before a next clock cycle.Type: GrantFiled: September 28, 2016Date of Patent: December 4, 2018Assignee: Mellanox Technologies, Ltd.Inventors: Andrew Carlson, Carl Ramey
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Publication number: 20180091125Abstract: An integrated circuit and method are described for compensating for voltage droop on an integrated circuit using a power supply voltage monitoring circuit and a high-resolution adaptive clock stretching circuit. In some example embodiments, the method includes monitoring power supply voltage on an integrated circuit, detecting a voltage droop such as a dynamic loss of power supply in the integrated circuit, and stretching a current clock cycle, according to the detected voltage droop, to provide more time for logic on the integrated circuit to complete before a next clock cycle.Type: ApplicationFiled: September 28, 2016Publication date: March 29, 2018Inventors: Andrew Carlson, Carl Ramey
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Patent number: 7620954Abstract: Each processor in a distributed shared memory system has an associated memory and a coherence directory. The processor that controls a memory is the Home processor. Under certain conditions, another processor may obtain exclusive control of a data block by issuing a Load Lock instruction, and obtaining a writeable copy of the data block that is stored in the cache of the Owner processor. If the Owner processor does not complete operations on the writeable copy of the data prior to the time that the data block is displaced from the cache, it issues a Victim To Shared message, thereby indicating to the Home processor that it should remain a sharer of the data block. In the event that another processor seeks exclusive rights to the same data block, the Home processor issues an Invalidate message to the Owner processor.Type: GrantFiled: August 8, 2001Date of Patent: November 17, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Matthew C. Mattina, Carl Ramey, Bongjin Jung, Judson Leonard
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Patent number: 7552241Abstract: The present invention relates to a method and system for managing I/O interfaces with an array of multicore processor resources in a semiconductor chip. The I/O interfaces are connected to the processor resources through an I/O shim. An I/O interface sends a dataframe to the I/O shim. The I/O interface packetizes data to form the dataframe, based on an I/O protocol. The dataframe includes a header and the data. The I/O shim identifies a command corresponding to the dataframe by using one or more of the processor resources. The command includes a set of tasks. Subsequently, the set of tasks is executed on the data.Type: GrantFiled: May 18, 2007Date of Patent: June 23, 2009Assignee: Tilera CorporationInventor: Carl Ramey