Patents by Inventor Carlos A. Paz de Araujo

Carlos A. Paz de Araujo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6706585
    Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: March 16, 2004
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo
  • Publication number: 20040046198
    Abstract: A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.
    Type: Application
    Filed: September 19, 2003
    Publication date: March 11, 2004
    Applicant: Symetrix Corporation
    Inventors: Vikram Joshi, Narayan Solayappan, Carlos A. Paz de Araujo, Larry D. McMillan
  • Publication number: 20040047174
    Abstract: A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.
    Type: Application
    Filed: October 9, 2003
    Publication date: March 11, 2004
    Inventors: Zheng Chen, Vikram Joshi, Myoungho Lim, Carlos A. Paz de Araujo, Larry D. McMillan, Yoshihisa Kato, Tatsuo Otsuki, Yasuhiro Shimada
  • Patent number: 6686489
    Abstract: A liquid precursor for forming a transparent metal oxide thin film comprises a first organic precursor compound. In one embodiment, the liquid precursor is for making a conductive thin film. In this embodiment, the liquid precursor contains a first metal from the group including tin, antimony, and indium dissolved in an organic solvent. The liquid precursor preferably comprises a second organic precursor compound containing a second metal from the same group. Also, the liquid precursor preferably comprises an organic dopant precursor compound containing a metal selected from the group including niobium, tantalum, bismuth, cerium, yttrium, titanium, zirconium, hafnium, silicon, aluminum, zinc and magnesium. Liquid precursors containing a plurality of metals have a longer shelf life. The addition of an organic dopant precursor compound containing a metal, such as niobium, tantalum or bismuth, to the liquid precursor enhances control of the conductivity of the resulting transparent conductor.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: February 3, 2004
    Assignee: Symetrix Corporation
    Inventors: Jolanta Celinska, Carlos A. Paz de Araujo, Joseph D. Cuchiaro, Jeffrey W. Bacon, Larry D. McMillan
  • Patent number: 6664115
    Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a taxis orientation to the final crystal, and results in improved thin-film electrical properties.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: December 16, 2003
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Masamichi Azuma, Carlos A. Paz de Araujo
  • Patent number: 6660536
    Abstract: A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between two electrodes in an annealing apparatus and voltage sufficient to polarize the ferroelectric thin film material in the direction of the electrical field is supplied to the electrodes during the anneal and as the film cools. Alternatively, probes are connected to the electrodes of a partially completed integrated circuit device and voltage sufficient to polarize the ferroelectric material is applied while annealing the material and as it cools. The anneal may be a furnace anneal or an RTP anneal.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: December 9, 2003
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Uchiyama, Carlos A. Paz de Araujo
  • Patent number: 6653156
    Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: November 25, 2003
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichiro Hayashi, Tatsuo Otsuki, Carlos A. Paz de Araujo
  • Publication number: 20030207470
    Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a C-axis orientation to the final crystal, and results in improved thin-film electrical properties.
    Type: Application
    Filed: July 5, 2001
    Publication date: November 6, 2003
    Applicants: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Masamichi Azuma, Carlos A. Paz De Araujo
  • Publication number: 20030203513
    Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.
    Type: Application
    Filed: April 2, 2003
    Publication date: October 30, 2003
    Applicants: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo
  • Patent number: 6639262
    Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: October 28, 2003
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Carlos A. Paz de Araujo, Masamichi Azuma, Larry D. McMillan, Koji Arita
  • Publication number: 20030157766
    Abstract: A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between two electrodes in an annealing apparatus and voltage sufficient to polarize the ferroelectric thin film material in the direction of the electrical field is supplied to the electrodes during the anneal and as the film cools. Alternatively, probes are connected to the electrodes of a partially completed integrated circuit device and voltage sufficient to polarize the ferroelectric material is applied while annealing the material and as it cools. The anneal may be a furnace anneal or an RTP anneal.
    Type: Application
    Filed: February 21, 2002
    Publication date: August 21, 2003
    Applicant: Symetrix Corporation and Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Uchiyama, Carlos A. Paz de Araujo
  • Patent number: 6607980
    Abstract: A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid temperature pulsing anneal (“RPA”) technique with a ramp rate of 30° C./second at a hold temperature of 650° C. for a holding time of 30 minutes. The RPA technique includes applying a plurality of rapid-temperature heat pulses in sequence.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: August 19, 2003
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Uchiyama, Carlos A. Paz de Araujo, Keisuke Tanaka
  • Publication number: 20030152813
    Abstract: An integrated circuit includes a layered superlattice material including one or more of the elements cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium. These elements may either be A-site elements or superlattice generator elements in the layered superlattice material. In one embodiment, one or more of these elements substitute for bismuth in a bismuth layered material. They also are preferably used in combination with one or more of the following elements: strontium, calcium, barium, bismuth, cadmium, lead, titanium, tantalum, hafnium, tungsten, niobium, zirconium, bismuth, scandium, yttrium, lanthanum, antimony, chromium, thallium, oxygen, chlorine, and fluorine. Some of these materials are ferroelectrics that crystallize at relatively low temperatures and are applied in ferroelectric non-volatile memories.
    Type: Application
    Filed: November 29, 2001
    Publication date: August 14, 2003
    Applicant: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Larry D. McMillan, Narayan Solayappan
  • Publication number: 20030132470
    Abstract: A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory capacitor is removed by etching to form a moat region. A nonconductive oxygen barrier layer is deposited to cover the sidewall and bottom of the moat. The nonconductive oxygen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a substantially continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer, the nonconductive oxygen barrier, and the conductive diffusion barrier substantially completely envelop the capacitor, in particular a ferroelectric thin film in the capacitor.
    Type: Application
    Filed: January 22, 2003
    Publication date: July 17, 2003
    Applicant: Symetrix Corporation
    Inventors: Vikram Joshi, Narayan Solayappan, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 6582972
    Abstract: A thin film of precursor for forming a layered superlattice material is applied to an integrated circuit substrate, then a strong oxidizing agent is applied at low temperature in a range of from 100° C. to 300° C. to the precursor thin film, thereby forming a metal oxide thin film. The strong oxidizing agent may be liquid or gaseous. An example of a liquid strong oxidizing agent is hydrogen peroxide. An example of a gaseous strong oxidizing agent is ozone. The metal oxide thin film is crystallized by annealing at elevated temperature in a range of from 500° C. to 700° C., preferably not exceeding 650° C., for a time period in a range of from 30 minutes to two hours. Annealing is conducted in an oxygen-containing atmosphere, preferably including water vapor. Treatment by ultraviolet (UV) radiation may precede annealing. RTP in a range of from 500° C. to 700° C. may precede annealing.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: June 24, 2003
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Vikram Joshi, Jolanta Celinska, Narayan Solayappan, Larry D. McMillan, Carlos A. Paz de Araujo, Koji Arita
  • Publication number: 20030102531
    Abstract: A nonconductive hydrogen barrier layer completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. The nonconductive hydrogen barrier layer and a conductive diffusion barrier beneath the capacitor together provide a continuous diffusion barrier between the capacitor and a switch. Also, the nonconductive hydrogen barrier layer and the conductive diffusion barrier continuously envelop the capacitor, in particular a ferroelectric thin film in the capacitor. Preferably, a nonconductive “buried” diffusion barrier layer is disposed over an extended area, providing a continuous diffusion barrier between the capacitor and the switch. A preferred fabrication method comprises forming a thin stack-electrode layer on a capacitor dielectric layer, and then etching the substrate to form self-aligning capacitor stacks.
    Type: Application
    Filed: November 22, 2002
    Publication date: June 5, 2003
    Applicant: Symetrix Corporation
    Inventors: Vikram Joshi, Narayan Solayappan, Carlos A. Paz de Araujo, Larry D. McMillan
  • Publication number: 20030098497
    Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.
    Type: Application
    Filed: November 29, 2001
    Publication date: May 29, 2003
    Applicant: Symetrix Corporation
    Inventors: Narayan Solayappan, Jolanta Celinska, Vikram Joshi, Carlos A. Paz de Araujo, Larry D. McMillan
  • Patent number: 6570202
    Abstract: A hydrogen barrier layer is formed above a ferroelectric thin film in an integrated circuit. The hydrogen barrier layer is directly over a protected segment of the ferroelectric thin film, while a sacrificial segment of the ferroelectric thin film extends laterally beyond the edges of the hydrogen barrier layer. The sacrificial segment absorbs hydrogen so that it cannot diffuse laterally into the protected segment of the ferroelectric thin film. After it absorbs hydrogen, the sacrificial segment is etched away to allow electrical connection to circuit layers below it. The ferroelectric thin film preferably comprises a layered superlattice compound. Excess bismuth or niobium added to the standard precursor solution of a strontium bismuth tantalum niobate compound helps to reduce hydrogen degradation of the ferroelectric properties.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: May 27, 2003
    Assignees: Symetrix Corporation, NEC Corporation
    Inventors: Joseph D. Cuchiaro, Akira Furuya, Carlos A. Paz de Araujo, Yoichi Miyasaka
  • Patent number: 6562678
    Abstract: A first reactant gas is flowed into a CVD reaction chamber containing a heated integrated circuit substrate. The first reactant gas contains a first precursor compound or a plurality of first precursor compounds, and the first precursor compound or compounds decompose in the CVD reaction chamber to deposit a coating containing metal atoms on the heated integrated circuit substrate. The coating is treated by RTP. Thereafter, a second reactant gas is flowed into a CVD reaction chamber containing the heated substrate. The second reactant gas contains a second precursor compound or a plurality of second precursor compounds, which decompose in the CVD reaction chamber to deposit more metal atoms on the substrate. Heat for reaction and crystallization of the deposited metal atoms to form a thin film of layered superlattice material is provided by heating the substrate during CVD deposition, as well as by selected rapid thermal processing (“RTP”) and furnace annealing steps.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: May 13, 2003
    Assignees: Symetrix Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Uchiyama, Narayan Solayappan, Carlos A. Paz de Araujo
  • Patent number: 6559469
    Abstract: An integrated circuit includes a layered superlattice material having the formula A1w1+a1A2w2+a2 . . . Ajwj+ajS1x1+s1S2x2+s2 . . . Skxk+skB1y1+b1B2y2+b2 . . . Blyl+blQz−q, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . B1 represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: May 6, 2003
    Assignee: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Larry D. McMillan, Vikram Joshi, Narayan Solayappan, Joseph D. Cuchiaro