Abstract: An electronic circuit is disclosed having a sample/hold amplifier connected to an adaptive amplifier. A plurality of such electronic circuits may be configured in an array of rows and columns. An input voltage vector may be compared with an analog voltage vector stored in a row or column of the array and the stored vector closest to the applied input vector may be identified and further processed. The stored analog value may be read out of the synapse by applying a voltage to a read line. An array of the readable synapses may be provided and used in conjunction with a dummy synapse to compensate for an error offset introduced by the operating characteristics of the synapses.

Abstract: A semiconductor structure for long-term learning includes a p-type silicon substrate or well having first and second spaced apart n-type regions formed therein. A polysilicon floating gate is separated from the surface of the silicon substrate by a layer of gate oxide. One edge of the polysilicon floating gate is aligned with the edge of the first n-type region such that the polysilicon floating gate does not appreciably overly the n-type region. The second n-type region lies beyond the edge of the polysilicon floating gate. The first n-type region, the silicon substrate, and the second n-type region form the collector, base, and emitter, respectively, of a lateral bipolar transistor.An alternate embodiment of a semiconductor long-term learning structure includes an n-type silicon substrate having a p-well region formed therein. An n-type region is formed within the well region.

Abstract: An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An ultraviolet window above the second capacitor allows the floating node to be charged, by the application of ultraviolet light, to a voltage which effectively cancels the input offset voltage.

Abstract: There is disclosed herein apparatus and a method for scanning information off a processing plane where the information is contained in a current signal having a very small amplitude and which can change signs and vary in amplitude by as much as five orders of magnitude. The preferred embodiment of the apparatus uses a pair of CMOS pass transistors connected to the individual processing elements and the row select lines. The pass transistors, when turned on, couple the output current from the processor containing the desired information to a column line. The column line is connected to a current to voltage converter in the form of a differential input amplifier having a non linear feedback circuit comprised of two diode connected CMOS transistors operating in the subthreshold region. The non linear feedback circuit provides an exponential transfer function which compresses the dynamic range of the output current from the processor to a smaller and more useable output range for an output voltage.

Abstract: An integrated sensor and analog processor for visual images is produced from an array of photoreceptor signals that are the space-time derivative of the photoreceptor outputs. Each photoreceptor output V.sub.R is first processed by an integrator having a predetermined time constant using a differential transconductance amplifier driving an integrating capacitor, and feeding the output signals V.sub.H back to the negative input, thereby generating a time integrated signal for each pixel of the array. The output terminal of the integrating amplifier is connected to a node that is coupled to the outputs of similar integrators of neighboring pixels by resistive connections thereby forming a spatially smoothed version of the image. At each node a differential amplifier takes the difference between the node potential and local receptor potential, whereby an output representing a first temporal derivative and second spatial derivative is computed.

Abstract: An electronically variable active analog delay line utilizes cascaded differential transconductance amplifiers with integrating capacitors and negative feedback from the output to the input of each noninverting amplifier. The delay of each section may be controlled through a conductor having distributed resistance connected at distributed points to the transconductance control terminal of the amplifiers with a controllable voltage gradient between the two ends of the conductor. Signals may be coupled in and added to a propagating signal using capacitors, or transconductance amplifiers which may also be of the differential transconductance type, particularly when coupling signals from a second delay line having substantially the same propagation velocity.

Abstract: An Electrically Erasable Programmable Logic Array (EEPLAS) (10,000) has an AND plasma (10,002) having a first array (10) of devices (Md11 through MDMN) each containing nonvolatile upper and lower memory cells that each have two serially connected field effect transistors (STUC, MTUC and STLC,MTLC), and an OR plane (10,004) having a second array (12,600) of memory cells with each cell being the same as the cells of the first array (10), and output inverting buffers (12,400). Bit lines (BLa1 through BLaN) of the first array (10) are coupled to word lines (WL1a through WLNa) of the second array (12,600). Each bit line (BLf1 through BLfx) of the second array (12,600) is connected to an input terminal of an inverting buffer (12,400). The outputs of the inverting buffers (12,400) serve as the Electrically Erasable Programmable Logic Array (10,000) output terminals. Each of the memory cells is an electrically erasable nonvolatile cell.

Abstract: A digital system is provided for synthesizing individual voices of musical instruments, which may then be combined into a musical composition. The system for a single voice is comprised of means for solving a system of simultaneous finite difference equations, where time is represented by real time in the computations. Musical sounds of the voice can then be produced by repetitiously solving the difference equations that model the instrument in real time, using an array of elemental means named "universal processing elements" (UPEs) interconnected by a matrix to each other and to external input and output terminals, and varying the sounds by varying the parameters. Each UPE is capable of computing Y=A+(B.times.M) from pipelined bit-serial inputs. The difference equations model a general linear filter, a second-order linear filter, a nonlinear polynomial function, and a random number (noise) generating function.

Abstract: An array of universal processing elements (UPEs) may be interconnected through a switching matrix in response to control words which are in turn produced by a programmed digital computer in response to commands from a keyboard or a data file, thereby routing the outputs of selected UPEs to other UPEs for further processing and/or combining a sound stream in digital form. The matrix is comprised of both local and global conductors, the local ones being available to selected groups of UPEs. Each UPE is implemented as a digital multiplier, preferably with pipelining, and each UPE is comprised of a plurality of stages, preferably implemented with an adder for computing the sum of a plus the Boolean logic function [b.multidot.m+d.multidot.m] and a multiplexer for forming the function [b.multidot.+d.multidot.m], where a, b, d and m are bits of the respective two's complement number A, B, D and M, whereby the entire array of stages in a UPE computes A+[B.times.M+D.times.(1-M)].

Abstract: A monodirectional logic form is provided using a bistable circuit of the set-rest type comprised of two cMOS inverters connected in parallel to a source of power (V.sub.dd) by a power-down p-channel MOS transistor. Each of the cMOS inverters is comprised of a first p-channel MOS transistor in source-drain-drain-source series with an n-channel MOS transistor. Two signal-pass n-channel MOS transistors are provided, one a signal-pass transistor connected as a series switch in a first signal (d) line to the input terminal of one cMOS inverter and the output terminal of the other cMOS inverter, and the other a signal-pass transistor connected as a series switch in a second complement signal (d) line to the input terminal of the other cMOS inverter and the output terminal of the one cMOS inverter.

Abstract: An optical mouse utilizing a linear array of photodiodes is provided with circuitry to correlate during each self-timed cycle a new image with a stored image from the previous cycle with the new image offset relative to the stored image one pixel (photodiode signal) to the right, one pixel to the left, and also with no offset. All three correlations are done at the same time in separate correlators. Decision as to motion to the right, to the left or no motion is made on the basis of maximum correlation output. The new image is not stored in a second store array for use during the next cycle until any motion is detected, but it is stored in a first store array during the cycle when half the precharged photodiodes discharge below a predetermined level in response to incident light. A new cycle is initiated by precharging the photodiodes when any decision of motion or no motion is made.

Abstract: A method and means for implementing the control structure of a computer comprising, for example the basic constructs of repetition, conditional execution, and nesting whereby, at any point, a machine language program can be decompiled into the English language source that produced it. The program is loaded into the memory of the machine in a manner to be location independent, so that each segment of a program may be debugged individually, if necessary, without affecting the balance of the program.

Abstract: An arrangement for organizing a computer is provided wherein all instructions in programs required for data processing, including memory addresses, are generated and processed outside of the central processor unit by using programmable logic arrays. Programmable logic arrays are also used for program supervision and for controlling peripheral hardware. Thus, the central processor unit is left to perform solely data processing and need not do any non-data processing functions.