Abstract: A display apparatus, a control method thereof and a recording medium are provided. The display apparatus includes: a display; a communicator configured to communicate with at least one external apparatus; and a processor configured to: control a user interface (UI) to be displayed on the display, the UI including a first item corresponding to the display apparatus and a second item corresponding to the at least one external apparatus and being displayed to distinguish between an external apparatus connected to the display apparatus and an external apparatus disconnected from the display apparatus, and, based on one of at least one of the second item being selected, control the external apparatus corresponding to the selected item to be connected to or disconnected from the display apparatus through the communicator.

Abstract: Provided is a solar cell including: a crystalline silicon semiconductor substrate having a specific radius of curvature; a plurality of microwire structures that extend from a first surface of the crystalline silicon semiconductor substrate in a vertical direction and are arranged spaced apart from each other; a first layer positioned on the first surface of the crystalline silicon semiconductor substrate and forming a P-N junction with the crystalline silicon semiconductor substrate; a first electrode part positioned on the first layer and connected to the first layer; a second layer positioned on a second surface of the crystalline silicon semiconductor substrate which is opposite the first surface; and a second electrode part positioned on the second layer and connected with the second layer.

Abstract: An overlay correction method may include obtaining a first central line of a lower pattern on a substrate, forming a photoresist pattern on the lower pattern, obtaining an ADI overlay value corresponding to a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern, obtaining an asymmetrical overlay value corresponding to a second distance between the first and second central lines, form an upper pattern using the photoresist pattern, obtaining an ACI overlay value corresponding to a third distance between the first central line and a fourth central line of the upper pattern, subtracting the ADI overlay value from the ACI overlay value to obtain a first overlay skew value, and adding the asymmetrical overlay value to the first overlay skew value to obtain a second overlay skew value.

Abstract: Provided are an extreme ultraviolet (EUV) exposure apparatus for improving an overlay error in a EUV exposure process, and an overlay correction method and a semiconductor device fabricating method using the exposure apparatus. The EUV exposure apparatus includes an EUV light source; a first optical system configured to emit EUV light from the EUV light source to an EUV mask; a second optical system configured to emit EUV light reflected from the EUV mask to a wafer; a mask stage; a wafer stage; and a control unit configured to control the mask stage and the wafer stage, wherein, based on a correlation between a first overlay parameter, which is one of parameters of overlay errors between layers on the wafer, and a second overlay parameter, which is another parameter, the first overlay parameter is corrected through correction of the second overlay parameter.

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Abstract: A method of manufacturing an integrated circuit (IC) device, the method including forming an underlayer on a feature layer such that the underlayer includes an acid generator; forming an acid-containing underlayer by generating a first acid from the acid generator; forming a photoresist film on the acid-containing underlayer; generating a second acid in a first area of the photoresist film by exposing the first area of the photoresist film; diffusing the first acid from the acid-containing underlayer into the first area of the photoresist film; and forming a photoresist pattern by developing the photoresist film.

Abstract: A method for fabricating a phase shift mask includes preparing a transmissive substrate on which a first mask region and a second mask region surrounding the first mask region are defined. In the first mask region, main patterns are formed having a first pitch in a first direction and a second direction perpendicular to the first direction. Each of the main patterns has a first area. In at least one row, assist patterns are formed at the first pitch to surround the main patterns. Each of the assist patterns has a second area less than the first area. In the second mask region, dummy patterns are formed in a plurality of rows. The dummy patterns surround the assist patterns at the first pitch. Each of the dummy patterns has a third area greater than the first area.

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Abstract: An EUV photomask having a main area and a scribe lane area and reflecting EUV light includes a reflective multilayer film and an absorption pattern, wherein the scribe lane area includes first and second lanes, wherein the first lane includes first and second sub-lanes extending in the same direction as an extending direction of the first lane, wherein the first sub-lane includes a first dummy pattern that is a portion of the absorption pattern, and the second sub-lane includes a second dummy pattern that is a portion of the absorption pattern, and when EUV light that is not absorbed by the first and second dummy patterns and is reflected by the reflective multilayer film is irradiated at least twice by overlapping a negative tone photoresist, an amount of light exceeds a threshold dose of light in the negative tone photoresist corresponding to the first lane.

Abstract: A semiconductor device manufacturing system includes a photolithography apparatus that performs exposure. On a semiconductor substrate including a chip area and a scribe lane area. An etching apparatus etches the exposed semiconductor substrate. An observing apparatus images the etched semiconductor substrate. A controller controls the photolithography apparatus and the etching apparatus. The controller generates a first mask pattern and provides the first mask pattern to the photolithography apparatus. The photolithography apparatus performs exposure on the semiconductor substrate using the first mask pattern. The etching apparatus performs etching on the exposed semiconductor substrate to provide an etched semiconductor substrate. The observing apparatus generates a first semiconductor substrate image by imaging the etched semiconductor substrate corresponding to the scribe lane area.

Abstract: A device may receive a request associated with adjusting the media output level of a sink device that is configured to output media content. The device may identify a source gain of a source device that is configured to provide the media content to the sink device, and a sink gain of the sink device. The device may identify a sink adjustment value for changing the sink gain based on the request for adjusting the media output level of the sink device, the source gain, and the sink gain. The device may transmit, to the sink device, a control signal to permit the sink gain to be changed based on the sink adjustment value. The media output level of the sink device is based on the source gain and the sink gain.

Abstract: Provided are an extreme ultraviolet (EUV) exposure apparatus for improving an overlay error in a EUV exposure process, and an overlay correction method and a semiconductor device fabricating method using the exposure apparatus. The EUV exposure apparatus includes an EUV light source; a first optical system configured to emit EUV light from the EUV light source to an EUV mask; a second optical system configured to emit EUV light reflected from the EUV mask to a wafer; a mask stage; a wafer stage; and a control unit configured to control the mask stage and the wafer stage, wherein, based on a correlation between a first overlay parameter, which is one of parameters of overlay errors between layers on the wafer, and a second overlay parameter, which is another parameter, the first overlay parameter is corrected through correction of the second overlay parameter.

Abstract: An engraving fixture for use with an engraver including a laser moveable along a linear X-axis path wherein the fixture comprises a base structure having two mutually extendable parts to assume different axial lengths thereby to accommodate objects of different lengths. The base can accommodate at an axial mid-point an auxiliary support for especially heavy objects. The base structure includes a support structure carrying the drive wheels and a stepper motor at one end, and a slidable passive support that can be placed at any location on the base member.

Abstract: Provided are an extreme ultraviolet (EUV) exposure apparatus for improving an overlay error in a EUV exposure process, and an overlay correction method and a semiconductor device fabricating method using the exposure apparatus. The EUV exposure apparatus includes an EUV light source; a first optical system configured to emit EUV light from the EUV light source to an EUV mask; a second optical system configured to emit EUV light reflected from the EUV mask to a wafer; a mask stage; a wafer stage; and a control unit configured to control the mask stage and the wafer stage, wherein, based on a correlation between a first overlay parameter, which is one of parameters of overlay errors between layers on the wafer, and a second overlay parameter, which is another parameter, the first overlay parameter is corrected through correction of the second overlay parameter.

Abstract: Provided are an extreme ultraviolet (EUV) exposure apparatus for improving an overlay error in a EUV exposure process, and an overlay correction method and a semiconductor device fabricating method using the exposure apparatus. The EUV exposure apparatus includes an EUV light source; a first optical system configured to emit EUV light from the EUV light source to an EUV mask; a second optical system configured to emit EUV light reflected from the EUV mask to a wafer; a mask stage; a wafer stage; and a control unit configured to control the mask stage and the wafer stage, wherein, based on a correlation between a first overlay parameter, which is one of parameters of overlay errors between layers on the wafer, and a second overlay parameter, which is another parameter, the first overlay parameter is corrected through correction of the second overlay parameter.

Abstract: The present disclosure relates to a fluorogenic pH-sensitive dye and a film for detecting pH using the fluorogenic pH-sensitive dye on a polymer film. The fluorogenic pH-sensitive dye includes an aryl compound having a sulfonyl group (—SO2) and an agarose compound covalently bonded to the sulfonyl group (—SO2) of the aryl compound.

Abstract: A foldable includes side members formed as a transverse central portion of the board, and folded respectively to form side surfaces of the box; an upper member formed to extend in an upper direction of the side members, and divided by a cutting line along a folding direction to form an upper surface of the box; and a lower member formed to extend in a lower direction of the side members, and divided by a cutting line along a folding direction to form a lower surface of the box.

Abstract: An overlay correction method may include obtaining a first central line of a lower pattern on a substrate, forming a photoresist pattern on the lower pattern, obtaining an ADI overlay value corresponding to a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern, obtaining an asymmetrical overlay value corresponding to a second distance between the first and second central lines, form an upper pattern using the photoresist pattern, obtaining an ACI overlay value corresponding to a third distance between the first central line and a fourth central line of the upper pattern, subtracting the ADI overlay value from the ACI overlay value to obtain a first overlay skew value, and adding the asymmetrical overlay value to the first overlay skew value to obtain a second overlay skew value.

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.