Abstract: An overlay correction method may include obtaining a first central line of a lower pattern on a substrate, forming a photoresist pattern on the lower pattern, obtaining an ADI overlay value corresponding to a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern, obtaining an asymmetrical overlay value corresponding to a second distance between the first and second central lines, form an upper pattern using the photoresist pattern, obtaining an ACI overlay value corresponding to a third distance between the first central line and a fourth central line of the upper pattern, subtracting the ADI overlay value from the ACI overlay value to obtain a first overlay skew value, and adding the asymmetrical overlay value to the first overlay skew value to obtain a second overlay skew value.

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

Abstract: An overlay correcting method capable of optimizing correction of an overlay within a scanner correction limit of a scanner of a scanner system, and a photolithography method, a semiconductor device manufacturing method and the scanner system which are based on the overlay correcting method are provided. The overlay correcting method includes collecting overlay data by measuring an overlay of a pattern; calculating correction parameters of the overlay by performing regularized regression using the overlay data, the regularized regression being based on a correction limit of the scanner such that the correction parameters fall within the correction limit of the scanner; and providing the correction parameters to the scanner.

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Abstract: Provided is a broadcast signal transmitting method including: generating a first bitstream including encoded data; generating a second bitstream by adding zero bits to the first bitstream, based on a difference between a modem data rate and a codec data rate; generating a third bitstream by encoding the second bitstream by using zero padding information about the zero bits; and transmitting a carrier signal generated by modulating the third bitstream.

Abstract: A display apparatus, a control method thereof and a recording medium are provided. The display apparatus includes: a display; a communicator configured to communicate with at least one external apparatus; and a processor configured to: control a user interface (UI) to be displayed on the display, the UI including a first item corresponding to the display apparatus and a second item corresponding to the at least one external apparatus and being displayed to distinguish between an external apparatus connected to the display apparatus and an external apparatus disconnected from the display apparatus, and, based on one of at least one of the second item being selected, control the external apparatus corresponding to the selected item to be connected to or disconnected from the display apparatus through the communicator.

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Abstract: A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region. The method includes forming a first layer on the substrate. The first layer has a first hole on the first region and a second hole on the second region. The method includes forming a second layer in the first hole and the second hole. The method includes forming a mask pattern on the second region of the substrate. The method includes polishing the second layer to form a pattern in the first hole and an overlay key pattern in the second hole. A top surface of the overlay key pattern is further from the substrate than a top surface of the pattern in the first hole.

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Abstract: Provided is a solar cell including: a crystalline silicon semiconductor substrate having a specific radius of curvature; a plurality of microwire structures that extend from a first surface of the crystalline silicon semiconductor substrate in a vertical direction and are arranged spaced apart from each other; a first layer positioned on the first surface of the crystalline silicon semiconductor substrate and forming a P-N junction with the crystalline silicon semiconductor substrate; a first electrode part positioned on the first layer and connected to the first layer; a second layer positioned on a second surface of the crystalline silicon semiconductor substrate which is opposite the first surface; and a second electrode part positioned on the second layer and connected with the second layer.

Abstract: A method of inspecting defects on a transparent substrate may include: selecting a gradient of an illumination optical system so that light incident on the transparent substrate has a first angle; selecting a gradient of a detection optical system so that an optical axis of the detection optical system located over the transparent substrate has a second angle, which is equal to or less than the first angle; adjusting a position of at least one of the illumination optical system, the transparent substrate, and the detection optical system so that a field-of-view of the detection optical system covers a first region where the light meets a first surface of the transparent substrate and does not cover a second region where light meets a second surface of the transparent substrate, the second surface being opposite to the first surface; illuminating the transparent substrate; and detecting light scattered from the transparent substrate.

Abstract: A method and apparatus for generating a preamble symbol in an Orthogonal Frequency Division Multiplexing (OFDM) system by generating a first main body sequence in a time domain by performing an inverse fast Fourier transform (IFFT) on a preset sequence in a frequency domain, generating a first postfix by copying samples in a preset section in the first main body sequence, generating a first prefix by copying samples in at least a portion of a section remaining by excluding the preset section from the first main body sequence, and generating a plurality of symbols, based on a combination of the first main body sequence, the first prefix, and the first postfix.

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Abstract: A method for fabricating a phase shift mask includes preparing a transmissive substrate on which a first mask region and a second mask region surrounding the first mask region are defined. In the first mask region, main patterns are formed having a first pitch in a first direction and a second direction perpendicular to the first direction. Each of the main patterns has a first area. In at least one row, assist patterns are formed at the first pitch to surround the main patterns. Each of the assist patterns has a second area less than the first area. In the second mask region, dummy patterns are formed in a plurality of rows. The dummy patterns surround the assist patterns at the first pitch. Each of the dummy patterns has a third area greater than the first area.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an L1 signaling generator configured to generate L1 signaling including first information and second information; a frame generator configured to generate a frame including a payload including a plurality of sub frames; and a signal processor configured to insert a preamble including the L1 signaling in the frame and transmit the frame. The first information includes information required for decoding a first sub frame among the plurality of sub frames. Therefore, a processing delay in a receiving apparatus is reduced.

Abstract: A method of inspecting defects of a transparent substrate may include: illuminating a transparent substrate; calculating an incidence angle range of light so that a first region where the light meets a first surface of the transparent substrate and a second region where light meets a second surface being opposite the first surface of the transparent substrate do not overlap each other; adjusting an incidence angle according to the incidence angle range; adjusting a position of a first detector so that a first field-of-view of the first detector covers the first region and does not cover the second region; adjusting a position of a second detector so that a second field-of-view of the second detector covers the second region and does not cover the first region; and obtaining a first image of the first region and a second image of the second region from the first and second detector, respectively.

Abstract: A device may receive a request associated with adjusting the media output level of a sink device that is configured to output media content. The device may identify a source gain of a source device that is configured to provide the media content to the sink device, and a sink gain of the sink device. The device may identify a sink adjustment value for changing the sink gain based on the request for adjusting the media output level of the sink device, the source gain, and the sink gain. The device may transmit, to the sink device, a control signal to permit the sink gain to be changed based on the sink adjustment value. The media output level of the sink device is based on the source gain and the sink gain.

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Abstract: A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting material layer to form recess patterns, forming conductor patterns in the recess patterns, removing a portion of an upper portion of the supporting material layer for causing upper portions of the conductor patterns to protrude, forming a block copolymer layer on the supporting material layer, processing the block copolymer layer to phase-separate the block copolymer layer into a plurality of block parts, selectively removing some of the phase-separated plurality of block parts, and removing the supporting material layer to expose the mold layer at a position corresponding to each of the removed block parts may be provided.