Patents by Inventor CHAN-SIC YOON
CHAN-SIC YOON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200312845Abstract: A semiconductor device includes a substrate having a first region and a second region. A device isolation layer is disposed in the substrate between the first region and the second region. The device isolation layer includes a buried dielectric layer in a trench that is recessed from a top surface of the substrate. A first liner layer is between the trench and the buried dielectric layer. A semiconductor layer is disposed on a top surface of the substrate of the first region. A first gate pattern is disposed on the semiconductor layer. A protrusion is disposed on a top surface of the device isolation layer.Type: ApplicationFiled: October 25, 2019Publication date: October 1, 2020Inventors: CHAN-SIC YOON, DONGOH KIM
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Patent number: 10790186Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.Type: GrantFiled: May 21, 2018Date of Patent: September 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jiseok Hong, Chan-Sic Yoon, Ilyoung Moon, Jemin Park, Kiseok Lee, Jung-Hoon Han
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Patent number: 10784266Abstract: An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.Type: GrantFiled: November 6, 2018Date of Patent: September 22, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-oh Kim, Ki-seok Lee, Chan-sic Yoon, Je-min Park, Woo-song Ahn
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Publication number: 20200295013Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.Type: ApplicationFiled: June 2, 2020Publication date: September 17, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ki Wook Jung, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Seok Lee, Ho In Lee, Ju Yeon Jang, Je Min Park, Jin Woo Hong
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Patent number: 10748910Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.Type: GrantFiled: August 2, 2018Date of Patent: August 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-Sic Yoon, Dongoh Kim, Kiseok Lee, Sunghak Cho, Jemin Park
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Patent number: 10679997Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.Type: GrantFiled: April 23, 2019Date of Patent: June 9, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ki Wook Jung, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Seok Lee, Ho In Lee, Ju Yeon Jang, Je Min Park, Jin Woo Hong
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Publication number: 20200135850Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.Type: ApplicationFiled: December 18, 2019Publication date: April 30, 2020Inventors: Chan-sic Yoon, Ho-in Lee, Ki-seok Lee, Je-min Park
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Publication number: 20200091305Abstract: An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer.Type: ApplicationFiled: May 7, 2019Publication date: March 19, 2020Inventors: Chan-sic YOON, Dong-oh KIM, Je-min PARK, Ki-seok LEE
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Patent number: 10541302Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.Type: GrantFiled: January 29, 2018Date of Patent: January 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-sic Yoon, Ho-in Lee, Ki-seok Lee, Je-min Park
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Publication number: 20190355728Abstract: An integrated circuit device includes: a substrate having a cell array area, which includes a first active region, and a peripheral circuit area, which includes a second active region; a direct contact connected to the first active region in the cell array area; a bit line structure connected to the direct contact in the cell array area; and a peripheral circuit gate structure on the second active region in the peripheral circuit area, wherein the peripheral circuit gate structure includes two doped semiconductor layers each being doped with a charge carrier impurity having different doping concentrations from each other.Type: ApplicationFiled: November 6, 2018Publication date: November 21, 2019Inventors: Dong-oh Kim, Ki-seok Lee, Chan-sic Yoon, Je-min Park, Woo-song Ahn
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Publication number: 20190326278Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.Type: ApplicationFiled: February 28, 2019Publication date: October 24, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kiseok LEE, Chan-Sic YOON, Dongoh KIM, Myeong-Dong LEE
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Publication number: 20190287977Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.Type: ApplicationFiled: May 22, 2019Publication date: September 19, 2019Inventors: Kiseok LEE, Chan-Sic YOON, Augustin HONG, Keunnam KIM, Dongoh KIM, Bong-Soo KIM, Jemin PARK, Hoin LEE, Sungho JANG, Kiwook JUNG, Yoosang HWANG
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Publication number: 20190252393Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.Type: ApplicationFiled: April 23, 2019Publication date: August 15, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Ki Wook JUNG, Dong Oh KIM, Seok Han PARK, Chan Sic YOON, Ki Seok LEE, Ho ln LEE, Ju Yeon JANG, Je Min PARK, Jin Woo HONG
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Patent number: 10373961Abstract: A semiconductor device includes first wiring line patterns on a support layer, second wiring line patterns on the first wiring line patterns, and a multiple insulation pattern. The first wiring line patterns extend in a first direction and are spaced apart from each other in a second direction. The support layer includes first contact hole patterns between the first wiring line patterns that are spaced apart from each other in the first and second directions. The second wiring line patterns extend in the second direction perpendicular and are spaced apart from each other in the first direction. The multiple insulation pattern is on an upper surface of the support layer where the first contact hole patterns are not formed, arranged in a third direction perpendicular to the first direction and the second direction, and between the first wiring line patterns and the second wiring line patterns.Type: GrantFiled: January 31, 2018Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTDInventors: Chan-sic Yoon, Ki-seok Lee, Jung-hyun Kim, Je-min Park
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Publication number: 20190214391Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.Type: ApplicationFiled: August 2, 2018Publication date: July 11, 2019Inventors: Chan-Sic Yoon, Dongoh Kim, Kiseok Lee, Sunghak Cho, Jemin Park
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Patent number: 10332842Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.Type: GrantFiled: July 3, 2018Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kiseok Lee, Sooho Shin, Juik Lee, Jun Ho Lee, Kwangmin Kim, Ilyoung Moon, Jemin Park, Bumseok Seo, Chan-Sic Yoon, Hoin Lee
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Patent number: 10332890Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.Type: GrantFiled: July 18, 2017Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kiseok Lee, Chan-Sic Yoon, Augustin Hong, Keunnam Kim, Dongoh Kim, Bong-Soo Kim, Jemin Park, Hoin Lee, Sungho Jang, Kiwook Jung, Yoosang Hwang
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Patent number: 10332894Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.Type: GrantFiled: December 1, 2017Date of Patent: June 25, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ki Wook Jung, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Seok Lee, Ho In Lee, Ju Yeon Jang, Je Min Park, Jin Woo Hong
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Patent number: 10332831Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.Type: GrantFiled: June 30, 2017Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Augustin Jinwoo Hong, Dae-Ik Kim, Chan-Sic Yoon, Ki-Seok Lee, Dong-Min Han, Sung-Ho Jang, Yoo-Sang Hwang, Bong-Soo Kim, Je-Min Park
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Patent number: 10325802Abstract: A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.Type: GrantFiled: September 22, 2017Date of Patent: June 18, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho In Lee, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Wook Jung, Jinwoo Augustin Hong, Je Min Park, Ki Seok Lee, Ju Yeon Jang