Patents by Inventor CHAN-SIC YOON
CHAN-SIC YOON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10312105Abstract: A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another.Type: GrantFiled: May 18, 2017Date of Patent: June 4, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-Sic Yoon, Jiung Pak, Kiseok Lee, Chan Ho Park, Hyeonok Jung
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Patent number: 10283360Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.Type: GrantFiled: February 1, 2018Date of Patent: May 7, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan Sic Yoon, Ki Seok Lee, Dong Oh Kim, Yong Jae Kim
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Publication number: 20190122919Abstract: A method of fabricating a semiconductor device includes providing a substrate, and forming an interlayered insulating layer on the substrate. The method includes forming a preliminary via hole in the interlayered insulating layer. The method includes forming a passivation spacer on an inner side surface of the preliminary via hole. The method includes forming a via hole using the passivation spacer as an etch mask. The method includes forming a conductive via in the via hole. The passivation spacer includes an insulating material different from an insulating material included in the interlayered insulating layer.Type: ApplicationFiled: May 21, 2018Publication date: April 25, 2019Inventors: JISEOK HONG, CHAN-SIC YOON, ILYOUNG MOON, JEMIN PARK, KISEOK LEE, JUNG-HOON HAN
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Patent number: 10204825Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.Type: GrantFiled: August 2, 2017Date of Patent: February 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong Ryul Lee, Joong Chan Shin, Dong Jun Lee, Ho Ouk Lee, Ji Min Choi, Ji Young Kim, Chan Sic Yoon, Chang Hyun Cho
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Patent number: 10199328Abstract: A semiconductor device includes a first contact plug on a substrate, a first lower electrode disposed on the first contact plug and extended in a thickness direction of the substrate, a first supporter pattern on the first lower electrode and including an upper surface and a lower surface, the upper surface of the first supporter pattern being higher than a top surface of the first lower electrode, a dielectric film on the first lower electrode, the upper surface of the first supporter pattern and the lower surface of the first supporter pattern and an upper electrode disposed on the dielectric film.Type: GrantFiled: September 7, 2016Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan Sic Yoon, Ki Seok Lee
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Publication number: 20180350818Abstract: A semiconductor device includes first wiring line patterns on a support layer, second wiring line patterns on the first wiring line patterns, and a multiple insulation pattern. The first wiring line patterns extend in a first direction and are spaced apart from each other in a second direction. The support layer includes first contact hole patterns between the first wiring line patterns that are spaced apart from each other in the first and second directions. The second wiring line patterns extend in the second direction perpendicular and are spaced apart from each other in the first direction. The multiple insulation pattern is on an upper surface of the support layer where the first contact hole patterns are not formed, arranged in a third direction perpendicular to the first direction and the second direction, and between the first wiring line patterns and the second wiring line patterns.Type: ApplicationFiled: January 31, 2018Publication date: December 6, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Chan-sic YOON, Ki-seok LEE, Jung-hyun KIM, Je-min PARK
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Publication number: 20180350905Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.Type: ApplicationFiled: January 29, 2018Publication date: December 6, 2018Inventors: Chan-sic Yoon, Ho-in Lee, Ki-seok Lee, Je-min Park
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Publication number: 20180331046Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.Type: ApplicationFiled: July 3, 2018Publication date: November 15, 2018Inventors: Kiseok LEE, Sooho SHIN, Juik LEE, Jun Ho LEE, Kwangmin KIM, Ilyoung MOON, Jemin PARK, Bumseok SEO, Chan-Sic YOON, Hoin LEE
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Publication number: 20180233506Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.Type: ApplicationFiled: April 17, 2018Publication date: August 16, 2018Inventors: Chan-Sic YOON, Ho-In RYU, Ki-Seok LEE, Chang-Hyun CHO
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Patent number: 10050041Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.Type: GrantFiled: April 17, 2018Date of Patent: August 14, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-Sic Yoon, Ho-In Ryu, Ki-Seok Lee, Chang-Hyun Cho
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Publication number: 20180226411Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.Type: ApplicationFiled: December 1, 2017Publication date: August 9, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Ki Wook JUNG, Dong Oh KIM, Seok Han PARK, Chan Sic YOON, Ki Seok LEE, Ho In LEE, Ju Yeon JANG, Je Min PARK, Jin Woo HONG
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Patent number: 10026694Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.Type: GrantFiled: May 30, 2017Date of Patent: July 17, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kiseok Lee, Sooho Shin, Juik Lee, Jun Ho Lee, Kwangmin Kim, Ilyoung Moon, Jemin Park, Bumseok Seo, Chan-Sic Yoon, Hoin Lee
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Patent number: 10026614Abstract: A method for manufacturing a semiconductor device includes forming features of a first mold pattern on a substrate including a first region and a second region, and forming a first insulation layer covering the first mold pattern from the first region to the second region. The method further includes forming a photoresist pattern on the first insulation layer in the second region, forming a second insulation layer covering the first insulation layer in the first region and the photoresist pattern in the second region from the first region to the second region, etching the second insulation layer, removing the photoresist pattern, and forming a first double patterning technology pattern having a first width in the first region and a second DPT pattern having a second width in the second region, wherein the second width is different from the first width.Type: GrantFiled: October 12, 2016Date of Patent: July 17, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Chan Sic Yoon, Ki Seok Lee, Dong Oh Kim
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Publication number: 20180175143Abstract: A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.Type: ApplicationFiled: December 6, 2017Publication date: June 21, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Chan-sic YOON, Ki-seok Lee, Ki-wook Jung, Dong-oh Kim, Ho-in Lee, Je-min Park, Seok-han Park, Augustin Hong, Ju-yeon Jang, Hyeon-ok Jung, Yu-jin Seo
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Publication number: 20180175038Abstract: A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and second sealing films, such that an etch selectivity of the second sealing film is smaller than that of the first sealing film, patterning the first and second sealing films to expose the second region and a portion of the device isolation film, such that an undercut is defined under a lower surface of the second sealing film, forming a filling film filling the undercut, a thickness of the filling film being thicker on a side surface of the second sealing film than on an upper surface thereof, removing a portion of the filling film to form a filling spacer in the undercut, forming a high-k dielectric film and a metal film on the filling spacer, and patterning the high-k dielectric film and the metal film.Type: ApplicationFiled: September 22, 2017Publication date: June 21, 2018Inventors: Ho In LEE, Dong Oh KIM, Seok Han PARK, Chan Sic YOON, Ki Wook JUNG, Jinwoo Augustin HONG, Je Min PARK, Ki Seok LEE, Ju Yeon JANG
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Publication number: 20180158669Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, fowling a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.Type: ApplicationFiled: February 1, 2018Publication date: June 7, 2018Inventors: Chan Sic Yoon, Ki Seok Lee, Dong Oh Kim, Yong Jae Kim
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Publication number: 20180158871Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.Type: ApplicationFiled: July 18, 2017Publication date: June 7, 2018Inventors: Kiseok LEE, Chan-Sic YOON, Augustin HONG, Keunnam KIM, Dongoh KIM, Bong-Soo KIM, Jemin PARK, Hoin LEE, Sungho JANG, Kiwook JUNG, Yoosang HWANG
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Publication number: 20180158718Abstract: A method for fabricating a semiconductor device includes providing a substrate including a cell region including a bit line structure, a bit line spacer and a lower electrode and a peripheral circuit region including first to third impurity regions, forming an interlayer insulating film on the peripheral circuit region, forming a first metal layer on the interlayer insulating film, forming a first trench and a second trench in the first metal layer between the first and second impurity regions, the second trench is disposed between the second and third impurity regions and exposes the interlayer insulating film, forming a first capping pattern on the first trench to form an air gap in the first trench, filling the second trench with a first insulating material, and forming, on the first metal layer, a contact connected to the third impurity region.Type: ApplicationFiled: August 2, 2017Publication date: June 7, 2018Inventors: DONG RYUL LEE, Joong Chan SHIN, Dong Jun LEE, Ho Ouk LEE, Ji Min CHOI, Ji Young KIM, Chan Sic YOON, Chang Hyun CHO
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Publication number: 20180158773Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.Type: ApplicationFiled: June 30, 2017Publication date: June 7, 2018Inventors: AUGUSTIN JINWOO HONG, DAE-IK KIM, CHAN-SIC YOON, Kl-SEOK LEE, DONG-MIN HAN, SUNG-HO JANG, YOO-SANG HWANG, BONG-SOO KIM, JE-MIN PARK
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Patent number: 9985034Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.Type: GrantFiled: December 29, 2015Date of Patent: May 29, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chan-Sic Yoon, Ho-In Ryu, Ki-Seok Lee, Chang-Hyun Cho