Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.

Abstract: An integrated circuit assembly including a first die including a device side and a backside opposite the device side; and a second die including a plurality of fluidly accessible channels therein, wherein the second die is coupled to a backside of the first die. A method of fabricating an integrated circuit assembly including coupling a first die to a second die, wherein the first die includes a device side and an opposite backside, wherein the device side includes a plurality of integrated circuits and wherein the second die includes a plurality of fluidly accessible channels therein.

Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.

Abstract: A semiconductor device that has a semiconductor die coupled to a substrate. A mold compound encapsulates the semiconductor die, and at least one thermal conductive material section extends from adjacent the semiconductor die through the mold compound. The at least one conductive material section thus conveys heat from the semiconductor die through the mold compound.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.

Abstract: An integrated circuit assembly including a first die including a device side and a backside opposite the device side; and a second die including a plurality of fluidly accessible channels therein, wherein the second die is coupled to a backside of the first die. A method of fabricating an integrated circuit assembly including coupling a first die to a second die, wherein the first die includes a device side and an opposite backside, wherein the device side includes a plurality of integrated circuits and wherein the second die includes a plurality of fluidly accessible channels therein.

Abstract: Disclosed embodiments include composite compliant pillars in a micro-structure array that extend at a non-orthogonal angle from a heat-sink base. The array is deployed against an integrated-circuit device package to deflect the composite compliant pillar array under conditions where heat-transfer performance is agnostic to dynamic non-planarity of the integrated-circuit device package.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.

Abstract: An integrated circuit die includes a device side and a backside opposite the device side, wherein the backside includes a heat transfer enhancement configuration formed therein or a heat transfer enhancement structure formed thereon each of which enhance a heat transfer area or a boiling nucleation site density over a planar backside surface. A method of forming an integrated circuit assembly includes disposing a heat exchanger on a multi-chip package, the multi-chip package including at least one integrated circuit die including a device side and an opposite backside includes a heat transfer enhancement configuration formed therein or a heat enhancement structure formed thereon; and contacting the backside of the at least one integrated circuit die with water or other cooling fluids, such as a mixture of water and antifreeze, alcohol, inert fluorinated hydrocarbon, helium, and/or other suitable cooling fluid (either liquid or gas).

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging.

Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a first die, a second die, and an integrated heat spreader. The integrated heat spreader may include a first surface. The first surface may define a first indentation located in between the first die and the second die.

Abstract: A semiconductor device that has a semiconductor die coupled to a substrate. A mold compound encapsulates the semiconductor die, and at least one thermal conductive material section extends from adjacent the semiconductor die through the mold compound. The at least one conductive material section thus conveys heat from the semiconductor die through the mold compound.

Abstract: Described herein are microelectronics packages and methods for manufacturing the same. The microelectronics package may include a first die, a second die, and an integrated heat spreader. The integrated heat spreader may include a first surface. The first surface may define a first indentation located in between the first die and the second die.

Abstract: A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging.

Abstract: A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.

Abstract: An apparatus is described that includes a first semiconductor die. A second semiconductor die is stacked on the first semiconductor die. The first semiconductor die has a larger surface area than the second semiconductor die such that there exists a peripheral region of the first semiconductor die that is not covered by the second semiconductor die. The apparatus includes thermally conductive material above the second semiconductor die. The apparatus includes a compound mold between the thermally conductive material and both the second semiconductor die and the peripheral region of the first semiconductor die. The apparatus includes a thermally conductive structure extending through the compound mold that thermally couples the peripheral region to the thermally conductive material.

Abstract: A thermal interface may include a wired network made of a first TIM, and a second TIM surrounding the wired network. A heat spreader lid may include a wired network attached to an inner surface of the heat spreader lid. An IC package may include a heat spreader lid placed over a first electronic component and a second electronic component. A first thermal interface may be formed between the first electronic component and the inner surface of the heat spreader lid, and a second thermal interface may be formed between the second electronic component and the inner surface of the heat spreader lid. The first thermal interface may include a wired network of a first TIM surrounded by a second TIM, while the second thermal interface may include the second TIM, without a wired network of the first TIM. Other embodiments may be described and/or claimed.