Abstract: An active rectifier and a wireless power receiver including the active rectifier are provided. According to an aspect, an active rectifier may include: a first loop configured to provide voltage when the phase of an input signal is positive; and a second loop configured to provide voltage when the phase of the input signal is negative, wherein the first loop and the second loop include a delay locked loop configured to compensate for reverse current leakage due to a delay of a switch included therein.

Abstract: A communication apparatus and a low noise amplifying method. The communication apparatus includes a gain adjusting unit to adjust a gain of an input signal; a combiner to generate an output signal using the signal gain-adjusted at the gain adjusting unit; and a feedback unit which provides a feedback signal, which is generated using the output signal generated at the combiner, to an input stage. Accordingly, various frequency bands defined in the wireless standards can be supported. Since the load impedance is generated without resistance, the manufacturing cost and the product size can be reduced.

Abstract: A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes.

Abstract: A filter cut-off frequency correction circuit, inputted with a step function increasing from a first voltage to a second voltage, comprises a linear passive filter, for integrating the step function to obtain a third voltage; a first comparator, outputting a first high-level signal when the third voltage is greater than a first predetermined reference voltage; a second comparator, outputting a second high-level signal in a first period from the time that the second voltage is applied to the time that the first comparator outputs the first high-level signal; a counter, for counting a number of clock pulses of a reference clock inputted in the first period; a digital block, for calculating a variation rate of time constant according to the number of clock pulses of the reference clock, and generating a correction code; and a filter, for correcting the cut-off frequency according to the correction code. The correction circuit can improve the speed of cut-off frequency adjustment.

Abstract: A filter cut-off frequency correction circuit, inputted with a step function increasing from a first voltage to a second voltage, comprises a linear passive filter, for integrating the step function to obtain a third voltage; a first comparator, outputting a first high-level signal when the third voltage is greater than a first predetermined reference voltage; a second comparator, outputting a second high-level signal in a first period from the time that the second voltage is applied to the time that the first comparator outputs the first high-level signal; a counter, for counting a number of clock pulses of a reference clock inputted in the first period; a digital block, for calculating a variation rate of time constant according to the number of clock pulses of the reference clock, and generating a correction code; and a filter, for correcting the cut-off frequency according to the correction code. The correction circuit can improve the speed of cut-off frequency adjustment.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes.

Abstract: A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.

Abstract: An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.

Abstract: A re-configurable low noise amplifier utilizing feedback capacitors is disclosed. The low noise amplifier has output transistors, capacitor switch cells, and capacitance distributors all in an output portion. The output transistors are for controlling selection of a specific frequency band in a wide band of frequencies. The capacitor switch cells are for adjusting a harmonic frequency for the specific frequency band. The capacitance distributor is for determining an amount of gain, and according to the gain, an output impedance feeds back to an input portion of the low noise amplifier for input matching. Since the output portion is at high impedance and suitable for a wide band of frequencies, input matching not only makes the low noise amplifier applicable to kinds of wireless communication standards, but also fulfills high gain and low noise figure.

Abstract: An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A subharmonic mixer, including an amplification unit for amplifying an input signal using at least one pair of amplification devices connected in parallel and a mixing unit for mixing the amplified signal with local oscillation signals from local oscillators is provided. The mixing unit performs switching over the amplification devices and at least four pairs of switching devices connected in parallel with each other, two pairs of switching devices being connected in parallel with each other and performing switching over one amplification device. The switching devices are supplied with local oscillation signals having different phases respectively, and two switching devices forming a pair are connected in parallel with each other and supplied with local oscillation signals having a 180° phase difference therebetween. Accordingly, the switching stage is formed with one stage, the operation is enabled with low-voltage power supplies, and noise performance, linearity, and gain are enhanced.

Abstract: A dual mode satellite signal receiver capable of supporting at least two global navigation satellite systems and a satellite signal receiving method are provided. The dual mode satellite signal receiver comprises a frequency synthesizer for generating a local oscillator signal based on a reference frequency; a mixer for mixing the local oscillator signal with a satellite signal and outputting the mixed signal as a signal of an intermediate frequency band; a first filter for filtering the signal output from the mixer to reject an image signal and output only an actual signal; a second filter for filtering the actual signal to output only a predetermined bandwidth according to a positioning mode; and an amplifier for amplifying the second filter output signal to a predetermined level and outputting the amplified signal.

Abstract: A re-configurable low noise amplifier utilizing feedback capacitors is disclosed. The low noise amplifier has output transistors, capacitor switch cells, and capacitance distributors all in an output terminal. The output transistors are for controlling selection of a specific frequency band in a wide band of frequencies. The capacitor switch cells are for adjusting a harmonic frequency for the specific frequency band. The capacitance distributor is for determining an amount of gain, and according to the gain, an output impedance feeds back to an input terminal of the low noise amplifier for input matching. Since the output terminal is at high impedance and suitable for a wide band of frequencies, input matching not only makes the low noise amplifier applicable to kinds of wireless communication standards, but also fulfills high gain and low noise figure.

Abstract: Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.