Abstract: Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

Abstract: Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits.

Abstract: A quadrature voltage controlled oscillator having low phase noise and excellent output swing characteristics includes a first voltage controlled oscillator for outputting a positive in-phase output signal and a negative in-phase output signal; a second voltage controlled oscillator for outputting a positive quadrature-phase output signal and a negative quadrature-phase output signal, the second voltage controlled oscillator having a symmetrical structure with the first voltage controlled oscillator and constituting a feedback loop together with the first voltage controlled oscillator; a first constant current source for supplying constant current to the first voltage controlled oscillator in response to the output signals; and a second constant current source for supplying constant current to the second voltage controlled oscillator in response to the output signals.

Abstract: A radio communication apparatus and a frequency generating method thereof the communication apparatus including a frequency generator to generate a plurality of local oscillator (LO) frequencies; and a mixer to convert a frequency of an input signal by mixing the input signal with at least two of the LO frequencies generated by the frequency generator. As the LO frequencies are generated using the single VCO to support the radio communication standard of the multiple bands, the circuit area can be reduced and the multimode and multiband can be supported with one chip.

Abstract: A communication apparatus and a low noise amplifying method. The communication apparatus includes a gain adjusting unit to adjust a gain of an input signal; a combiner to generate an output signal using the signal gain-adjusted at the gain adjusting unit; and a feedback unit which provides a feedback signal, which is generated using the output signal generated at the combiner, to an input stage. Accordingly, various frequency bands defined in the wireless standards can be supported. Since the load impedance is generated without resistance, the manufacturing cost and the product size can be reduced.

Abstract: A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.

Abstract: A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.

Abstract: A memory system having a stub-bus configuration transmits a free-running clock through the same path as data signals. A single clock domain is employed for both read and write operations. For both operations, the read or write clock signal is routed through the same transmission path as the data, thereby increasing system transfer rates by maximizing the window of data validity. In this manner, data bus utilization is increased due to the elimination of a need for a preamble interval for the strobe signal, and pin count on the memory module connectors is therefore reduced.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation.

Abstract: The present invention relates to a semiconductor circuit; and, more particularly, to a duty cycle correction circuit (hereinafter referred to as “DCC”). Furthermore, the present invention relates to an open-loop digital DCC. The duty cycle correction circuit according to the present invention includes: a delayer for delaying an input clock signal and for generating a plurality of delayed clock; a phase comparator for comparing the input clock signal with the plurality of delayed clock signals; a multiplexer for selecting one out of the delayed clock signals in response to an output signal of the phase comparator and for inverting the selected delay clock signals; and a phase combiner for combining the clock signal from the multiplexer and the input clock signal. Accordingly, the digital DCC according to the present invention is of an open loop without any DLL, the duty correction can be made within five clock periods after power-up.

Abstract: A subharmonic mixer, including an amplification unit for amplifying an input signal using at least one pair of amplification devices connected in parallel and a mixing unit for mixing the amplified signal with local oscillation signals from local oscillators is provided. The mixing unit performs switching over the amplification devices and at least four pairs of switching devices connected in parallel with each other, two pairs of switching devices being connected in parallel with each other and performing switching over one amplification device. The switching devices are supplied with local oscillation signals having different phases respectively, and two switching devices forming a pair are connected in parallel with each other and supplied with local oscillation signals having a 180° phase difference therebetween. Accordingly, the switching stage is formed with one stage, the operation is enabled with low-voltage power supplies, and noise performance, linearity, and gain are enhanced.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation.

Abstract: A quadrature voltage controlled oscillator having low phase noise and excellent output swing characteristics includes a first voltage controlled oscillator for outputting a positive in-phase output signal and a negative in-phase output signal; a second voltage controlled oscillator for outputting a positive quadrature-phase output signal and a negative quadrature-phase output signal, the second voltage controlled oscillator having a symmetrical structure with the first voltage controlled oscillator and constituting a feedback loop together with the first voltage controlled oscillator; a first constant current source for supplying constant current to the first voltage controlled oscillator in response to the output signals; and a second constant current source for supplying constant current to the second voltage controlled oscillator in response to the output signals.

Abstract: A method of operating a memory system including a plurality of memory devices coupled to a command address bus may be provided. In particular, a first memory device of the plurality of memory devices may be set to a first operating mode, and a second memory device of the plurality of memory devices may be set to a second operating mode different than the first operating mode. In addition, a read/write operation may be performed responsive to a read/write command address signal provided over the command address bus to the plurality of memory devices so that the first memory device operates according to the first operating mode during the read/write operation and so that the second memory device operates according to the second operating mode during the read/write operation. Related systems are also discussed.