Patents by Inventor Chang Yu

Chang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230261038
    Abstract: A capacitor structure is provided. The capacitor structure includes a first electrode and a second electrode. The first electrode includes a first segment and a third segment. The second electrode includes a second segment and a fourth segment, the second segment is interposed between the first segment and the third segment, and the third segment is interposed between the second segment and the fourth segment. A first distance is between the first segment and the second segment, and a second distance between the second segment and the third segment. The first distance is different from the second distance.
    Type: Application
    Filed: February 14, 2022
    Publication date: August 17, 2023
    Inventors: CHANG-YU HUANG, YI HSUAN LIN, CHIH-PIN HUNG
  • Patent number: 11722220
    Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Cheng-Yuan Kung, Hung-Yi Lin
  • Publication number: 20230230935
    Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.
    Type: Application
    Filed: March 21, 2023
    Publication date: July 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Ching, Shu-Shen Yeh, Chien-Hung Chen, Hui-Chang Yu, Yu-Min Cheng
  • Publication number: 20230220022
    Abstract: Disclosed are a novel therapeutic means effective and practical against cancer, and a novel substance useful as such a therapeutic means. Provided are novel peptides derived from a partial region of HMGN1, HMGN2, HMGN4 or HMGN5, and anti-cancer agents and anti-cancer effect enhancers containing the peptide as an active ingredient. The peptide of the present invention has an anti-tumor effect even independently, and exerts a remarkably excellent anti-tumor effect particularly when used in combination with an immune checkpoint regulator, or an anti-CD4 antibody or antigen-binding fragment thereof.
    Type: Application
    Filed: January 3, 2023
    Publication date: July 13, 2023
    Applicants: The University of Tokyo, ONO PHARMACEUTICAL CO., LTD., TOKYO UNIVERSITY OF SCIENCE FOUNDATION
    Inventors: Kouji MATSUSHIMA, Satoshi UEHA, Shungo DESHIMARU, Chang-Yu CHEN, Shoji YOKOCHI, Yoshiro ISHIWATA, Shiro SHIBAYAMA
  • Patent number: 11699631
    Abstract: Semiconductor device includes circuit substrate, first semiconductor die, thermal interface material, package lid. First semiconductor die is disposed on and electrically connected to circuit substrate. Thermal interface material is disposed on first semiconductor die at opposite side of first semiconductor die with respect to circuit substrate. Package lid extends over first semiconductor die and is bonded to the circuit substrate. Package lid includes roof, footing, and island. Roof extends along first direction and second direction perpendicular to first direction. Footing is disposed at peripheral edge of roof and protrudes from roof towards circuit substrate along third direction perpendicular to first direction and second direction. Island protrudes from roof towards circuit substrate and contacts thermal interface material on first semiconductor die. Island is disconnected from footing along second direction.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: July 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Hui-Chang Yu, Shyue-Ter Leu, Shin-Puu Jeng
  • Patent number: 11686532
    Abstract: The disclosure is related to a heat dissipation structure. The heat dissipation structure is adapted to accommodate a fluid and thermally contact a heat source. The heat dissipation structure includes a heat conductive plate and a channel arrangement. The heat conductive plate is configured to thermally contact the heat source. The channel arrangement is located on the heat conductive plate, and the channel arrangement includes a wider channel portion and a narrower channel portion. The wider channel portion is wider than the narrower channel portion, and the wider channel portion is connected to the narrower channel portion so that the channel arrangement forms a loop. The channel arrangement is configured to accommodate the fluid and allow the fluid to absorb heat generated by the heat source through the heat conductive plate so as to at least partially change phase of the fluid.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: June 27, 2023
    Assignee: COOLER MASTER CO., LTD.
    Inventors: Chi-Chuan Wang, Chang-Yu Hsieh, Shan-Yin Cheng, Hsiang-Fen Chou
  • Patent number: 11688690
    Abstract: A semiconductor device includes: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region includes multiple alternating well layers and barrier layers, wherein each of the barrier layers has a band gap, the active region further includes an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region, wherein the electron blocking region includes a band gap, and the band gap of the electron blocking region is greater than the band gap of one of the barrier layers; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the electron blocking region; a confinement layer between the fi
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: June 27, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Yung-Chung Pan, Chang-Yu Tsai, Ching-Chung Hu, Ming-Pao Chen, Chi Shen, Wei-Chieh Lien
  • Publication number: 20230196986
    Abstract: A pixel and a display device including the same are disclosed. The pixel includes a light emitting element, first through seventh transistors, and a first capacitor. The first transistor is connected between first and second nodes. The second transistor is connected between a data line and a fourth node and configured to be turned on by a first scan signal. The third transistor is connected between the first node and a third node and configured to be turned on by a second scan signal. The fourth transistor is connected between the fourth node and a third power line and configured to be turned on by a third scan signal. The fifth transistor is connected between the third node and the third power line and configured to be turned on by a fourth scan signal. The sixth transistor is connected between the first node and a fifth node and configured to be turned off by an emission control signal.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 22, 2023
    Inventors: Byung Chang YU, Hyun Joon KIM, Hae Min KIM, Myung Hoon PARK, Dong Hoon LEE
  • Publication number: 20230189388
    Abstract: This application provides a communication method and apparatus. The communication method and apparatus may be applied to an Internet of Vehicles system, a V2X system, and a device-to-device communication system. The method includes: obtaining first indication information and second indication information, where the first indication information indicates a first periodicity for receiving signaling and/or data and a second periodicity for not receiving signaling and data, and the second indication information indicates a first time unit for receiving signaling and/or data and a second time unit for not receiving signaling and data in the first periodicity; and determining to receive signaling and/or data in the first time unit.
    Type: Application
    Filed: October 28, 2022
    Publication date: June 15, 2023
    Inventors: Chang Yu, Junren Chang, Guowei Ouyang
  • Publication number: 20230178120
    Abstract: A method (for recycling charge from a first bit line of a memory device to a second bit line of the memory device) includes: before pre-filling the second bit line, momentarily closing switches to transfer a first charge from the first bit line which is involved in a first read operation to the second bit line which is involved subsequently in a second read operation; and each of the first bit line and the second bit line being served by a same sense amplifier.
    Type: Application
    Filed: February 7, 2023
    Publication date: June 8, 2023
    Inventors: Hung-Chang YU, Ta-Ching YEH
  • Publication number: 20230144521
    Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region comprises multiple alternating well layers and first barrier layers, wherein each of the first barrier layers has a band gap, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; a first electron blocking layer between the second semiconductor structure and the active region, wherein the first electron blocking layer having a band gap greater than the band gap of one of the first barrier layers; a first aluminum-containing layer between the first electron blocking layer and the active region, wherein the first aluminum-containing layer has a first thickness and a band gap greater than the band gap of the first electron blocking layer; and a second aluminum-conta
    Type: Application
    Filed: January 6, 2023
    Publication date: May 11, 2023
    Inventors: Chia-Ming LIU, Chang-Hua HSIEH, Yung-Chung PAN, Chang-Yu TSAI, Ching-Chung HU, Ming-Pao CHEN, Chi SHEN, Wei-Chieh LIEN
  • Patent number: 11637072
    Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Ching, Shu-Shen Yeh, Chien-Hung Chen, Hui-Chang Yu, Yu-Min Cheng
  • Patent number: 11629845
    Abstract: A clamp lamp could clamp a screen having a front surface and a rear surface is provided. The clamp lamp includes a first clip, a second clip and a light-emitting module. When the clamp lamp clamps an edge of the screen, the first and second clips abut on the front surface and the rear surface of the screen respectively. The light-emitting module is connected to the first clip and includes a casing, a light-emitting element and a light-reflecting element. The casing has a light outlet. The light-emitting element is disposed in the casing and configured to emit a light and reflect the light to illuminate the front of the front surface through the light outlet. The light-reflecting element has first and second reflecting surfaces connected to each other. The first reflecting surface has several reflecting points, each having a radius of curvature equal to or greater than 25 mm.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: April 18, 2023
    Assignee: Qisda Corporation
    Inventor: Chang-Yu Tsai
  • Publication number: 20230086858
    Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chin Lin, Hung-Chang Yu
  • Publication number: 20230081412
    Abstract: A training method for a neural network includes determining first disassembly paths of a plurality of first molecules, and obtaining a first cost dictionary based on the first disassembly paths of the first molecules. The method also includes determining molecular expression information of second molecules based on the first disassembly paths of the first molecules, and determining a plurality of third molecules from the second molecules, each of the third molecules representing a class of the second molecules. The method further includes obtaining a second cost dictionary based on second disassembly paths of the third molecules, and performing training based on the first cost dictionary and the second cost dictionary to obtain a target neural network. The target neural network being configured to output cost value information corresponding to a target molecule according to input molecular expression information of the target molecule.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 16, 2023
    Applicant: Tencent Technology (Shenzhen) Company Limited
    Inventors: Yue FU, Chang-Yu HSIEH, Benben LIAO, Jianye HAO, Shengyu ZHANG
  • Publication number: 20230072698
    Abstract: A device includes a single standard cell. The single standard cell includes a first transistor region including a first extended active region extending between a first side cell boundary and a second side cell boundary opposite the first side cell boundary, and includes a plurality of source regions and one drain region. The single standard cell further includes a second transistor region including a second extended active region extending between the first side cell boundary and the second side cell boundary, and includes a source region and a single drain region.
    Type: Application
    Filed: November 14, 2022
    Publication date: March 9, 2023
    Inventors: Lee-Chung LU, Li-Chun TIEN, Hui-Zhong ZHUANG, Chang-Yu WU
  • Publication number: 20230071568
    Abstract: This invention discloses a display panel including a first substrate, light emitting elements, a touch sensing structure and a conductive layer. The light emitting elements are disposed on the first substrate. The touch sensing structure is disposed on the first substrate and on a side away from a light emitting surface of the light emitting elements. The conductive layer is disposed between the light emitting elements and the first substrate and includes contacts or at least a portion of the touch sensing structure, and the light emitting elements and the contacts are electrically connected.
    Type: Application
    Filed: August 15, 2022
    Publication date: March 9, 2023
    Applicant: HANNSTAR DISPLAY CORPORATION
    Inventors: Jing-Xuan Chen, Cheng-Yen Yeh, Mu-Kai Kang, Sz-Kai Huang, Ming-Chang Yu
  • Patent number: 11600746
    Abstract: A semiconductor device comprises: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region, wherein the active region comprises multiple alternating well layers and barrier layers, the active region further comprises an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the first electron blocking layer; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies at a distance of between 15 nm and 60 nm from the upper surface of the active region.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: March 7, 2023
    Assignee: EPISTAR CORPORATION
    Inventors: Chia-Ming Liu, Chang-Hua Hsieh, Yung-Chung Pan, Chang-Yu Tsai, Ching-Chung Hu, Ming-Pao Chen, Chi Shen, Wei-Chieh Lien
  • Publication number: 20230060520
    Abstract: Disclosed are semiconductor packages and semiconductor devices. In one embodiment, a semiconductor package includes a package, a first integrated passive device, and a second integrated passive device. The first integrated passive device is disposed below the package. The second integrated passive device is disposed between the package and the first integrated passive device. The first integrated passive device is electrically connected to the package through the second integrated passive device.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Jung Tseng, Hui-Chang Yu
  • Patent number: 11594658
    Abstract: A light-emitting element is provided, including a semiconductor structure, a reflective structure, first insulating structures, a conductive structure, and first and second pads. The reflective structure is disposed on the semiconductor structure. The first insulating structure includes first and second insulating portions covering first and second portions respectively, and a gap exposes a third portion between the first and second portions. The conductive structure includes first and second conductive portion. The first conductive portion is disposed on the first insulating portion to contact the semiconductor structure. The second conductive portion is disposed on the second insulating portion to contact the third portion through the gap. The first and second pads are respectively disposed on the first and second conductive portions. Each of the structures below the first and second pads are in flat-type bonding to enhance stress resistance.
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: February 28, 2023
    Assignee: Lextar Electronics Corporation
    Inventors: Pei-Shiu Tsai, Yi-Ju Chen, Nai-Wei Hsu, Wei-Chang Yu