Patents by Inventor Chao-Sung Lai

Chao-Sung Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030216048
    Abstract: A method for fabricating a floating gate. A semiconductor substrate is provided, on which an insulating layer, conductive layer, and patterned hard mask layer are sequentially formed. The hard mask layer and the conductive layer are sequentially etched to form a trench. The exposed conductive layer is oxidized to form an oxide layer. The hard mask layer is removed. The conductive layer where not covered by the oxide layer is removed using the oxide layer as a mask.
    Type: Application
    Filed: April 8, 2003
    Publication date: November 20, 2003
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Shian-Jyh Lin, Chung-Lin Huang, Ming-Yuan Huang, Chao Sung Lai, Kuo-Chung Chen
  • Publication number: 20030216044
    Abstract: A method for forming bottle trenches. The method comprises providing a substrate formed with a pad stack layer on the top, and a deep trench with protective layer on the upper portions of sidewalls thereof, implanting ions into the lower portions of sidewalls and bottom of the trench not covered by the protective layer to amorphize the atomic structure of the sidewalls and bottom, oxidizing the amorphous sidewalls and bottom of the trench to form a bottle-shaped oxide layer thereon, and removing the bottle-shaped oxide layer.
    Type: Application
    Filed: May 7, 2003
    Publication date: November 20, 2003
    Applicant: Nanya Technology Corporation
    Inventors: Shian-Jyh Lin, Chao-Sung Lai
  • Patent number: 5567638
    Abstract: A method for suppressing boron penetration in a PMOS with a nitridized polysilicon gate includes steps of 1) growing a layer of gate oxide on a substrate, 2) forming at least one first polysilicon layer on the gate oxide layer, 3) nitridizing the first polysilicon layer, 4) forming a second polysilicon layer on the first polysilicon layer; and 5) implanting B-containing ions into the first and second polysilicon layers for constructing a PMOS structure wherein the nitridizing step suppresses a boron ion from penetration into the substrate. The present invention is characterized in nitridation on a polysilicon gate instead of a gate oxide which can effectively suppress boron penetration, avoid drawbacks resulting from nitridizing a gate oxide, and moreover, improve the reliability of the device owing to the slight nitridation effect in the polysilicon gate and the gate oxide.
    Type: Grant
    Filed: June 14, 1995
    Date of Patent: October 22, 1996
    Assignee: National Science Council
    Inventors: Yung-Hao Lin, Chao-Sung Lai, Chung-Len Lee, Tan-Fu Lei