Abstract: Techniques for updating an electrophoretic display or other integrating display are provided. A first image data representing the current optical state of the display is combined with a second image data representing the desired next optical state of the display along with a third data representing the charge history of the display to form a compact intermediate representation of the electrical drive signals required to transition the display. Such compact intermediate representations can be provided for each pixel of the display and stored in flash memory. Once determined, these representations of the drive signals can be rapidly replayed from flash memory and further processed to drive the display and affect the desired optical transition from current image to next image while correcting for DC imbalances.

Abstract: Techniques for updating an electrophoretic display or other integrating display are provided. A first image data representing the current optical state of the display is combined with a second image data representing the desired next optical state of the display along with a third data representing the charge history of the display to form a compact intermediate representation of the electrical drive signals required to transition the display. Such compact intermediate representations can be provided for each pixel of the display and stored in flash memory. Once determined, these representations of the drive signals can be rapidly replayed from flash memory and further processed to drive the display and affect the desired optical transition from current image to next image while correcting for DC imbalances.

Abstract: Techniques are disclosed for controlling an active matrix display using adaptive charge sharing. Separate voltages applied to each column control line correspond to the image data for setting the grayscale level of the respective pixels. Image data for one row of pixels are compared to the image data for another row of pixels on a column-by-column basis. If the image data for one or more columns changes from one row to the next by more than a threshold amount, charge sharing is activated between updating different rows for controlling the corresponding column control lines of the display. Charge sharing may be implemented by adding one or more capacitors that are switched with a block of column control lines, and a processor configured to compare the image data for successive rows, determine whether the criteria for charge sharing are met, and control the switches based on the determination.

Abstract: Described herein are systems and methods for stress avoidance and stress compensation in low power Liquid Crystal Displays (LCDs). In an exemplary embodiment, two or more transistors in series are used to hold charge on an LCD pixel. To avoid negative stress on the transistors, the transistors are alternately driven to an “off” state so that no one transistor sees a long “off” time. In another embodiment, stress on transistors of a display circuit are measured and controlled negative stress is applied to the transistors to compensate for the measured stress.

Abstract: Described herein are systems and methods for the reduction of power consumption and mitigation of device stress accumulation in low frequency refreshed Liquid Crystal Displays (LCDs). In an exemplary embodiment, two or more transistors in series are used to hold charge on an LCD pixel. To prevent negative stress on the transistors, the transistors are alternately driven to an “on” state so that no one transistor sees a long “off” time. In another embodiment, circuits and signaling waveforms for performing frame writing and stress mitigation are provided that minimize dynamic power consumption and static power consumption in peripheral ESD circuits.

Abstract: Described herein are systems and methods for the reduction of power consumption and mitigation of device stress accumulation in low frequency refreshed Liquid Crystal Displays (LCDs). In an exemplary embodiment, two or more transistors in series are used to hold charge on an LCD pixel. To prevent negative stress on the transistors, the transistors are alternately driven to an “on” state so that no one transistor sees a long “off” time. In another embodiment, circuits and signaling waveforms for performing frame writing and stress mitigation are provided that minimize dynamic power consumption and static power consumption in peripheral ESD circuits.

Abstract: Systems, apparatus and methods for acquiring code phase and multipath channel models in communication device. A fast Walsh transform engine is used to acquire a pseudo noise code phase and the pseudo noise code bit rate of a radiofrequency signal that has been broadcast. Multipath filter coefficients from the pseudo noise code phase and the pseudo noise code bit rate are recovered. A pseudo noise generator is initialized with the pseudo noise code phase acquired during the fast Walsh transform step. The pseudo noise code phase and pseudo noise code bit rate are tracked by a phase locked loop so that communication with the radiofrequency signal is maintained. Then, the received noise code phase and pseudo noise code bit rate are despread so that any data in the radiofrequency signal is recovered.

Abstract: A method is provided for scaling a source image to produce a destination image. According to the method, a local context metric is calculated from a local portion of the source image. A convolution kernel is generated from a plurality of available convolution kernels based on the calculated local context metric, and the generated convolution kernel is used to generate at least one pixel in the destination image. Also provided is an image scaling device that receives pixels of a source image and outputs pixels of a scaled destination image. The image scaling device includes a context sensor, a kernel generator, and a scaler. The context sensor calculates a local context metric based on local source image pixels, and the kernel generator generates a current convolution kernel from a plurality of available convolution kernels based on the local context metric calculated by the context sensor.

Abstract: Described herein are systems and methods for stress avoidance and stress compensation in low power Liquid Crystal Displays (LCDs). In an exemplary embodiment, two or more transistors in series are used to hold charge on an LCD pixel. To avoid negative stress on the transistors, the transistors are alternately driven to an “off” state so that no one transistor sees a long “off” time. In another embodiment, stress on transistors of a display circuit are measured and controlled negative stress is applied to the transistors to compensate for the measured stress.

Abstract: A communication system includes a receiver for receiving a serial bit stream from at least one communication channel, and a decoder, in communication with the receiver, for decoding words from the received serial bit stream, the words being defined at least in part by word boundaries in the received serial bit stream. The decoder contemporaneously synchronizes detection of bits and detection of the word boundaries in the received serial bit stream. The decoder preferably decodes digitized video signal information in the serial bit stream according to a Transition Minimized Differential Signalling protocol. The receiver and decoder are preferably part of an integrated circuit chip.

Abstract: A method, system and computer readable medium for transforming three dimensional (3D) color information into a color standard is described. A 3D cube defined by eight RGB color points representing the eight vertices of the 3D cube is stored. Each of the eight points represents one of the colors: red, yellow, white, magenta, blue, black, green and cyan. In addition, each of the eight points represents the difference between the capacity of a display and the color standard. The 3D cube is divided into six tetrahedrons and the tetrahedron corresponding to an input RGB pixel is selected. A 3×3 matrix based on the vertices of the selected tetrahedron is calculated. The 3×3 matrix is then multiplied by the components of the input RGB pixel to produce an output RGB pixel conforming to the color standard.

Abstract: A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal.

Abstract: A method, system and computer readable medium for transforming three dimensional (3D) color information into a color standard is described. A 3D cube defined by eight RGB color points representing the eight vertices of the 3D cube is stored. Each of the eight points represents one of the colors: red, yellow, white, magenta, blue, black, green and cyan. In addition, each of the eight points represents the difference between the capacity of a display and the color standard. The 3D cube is divided into six tetrahedrons and the tetrahedron corresponding to an input RGB pixel is selected. A 3×3 matrix based on the vertices of the selected tetrahedron is calculated. The 3×3 matrix is then multiplied by the components of the input RGB pixel to produce an output RGB pixel conforming to the color standard.

Abstract: A communication system includes a receiver for receiving a serial bit stream from at least one communication channel, and a decoder, in communication with the receiver, for decoding words from the received serial bit stream, the words being defined at least in part by word boundaries in the received serial bit stream. The decoder contemporaneously synchronizes detection of bits and detection of the word boundaries in the received serial bit stream. The decoder preferably decodes digitized video signal information in the serial bit stream according to a Transition Minimized Differential Signalling protocol. The receiver and decoder are preferably part of an integrated circuit chip.

Abstract: A method, system and computer readable medium for transforming three dimensional (3D) color information into a color standard is described. A 3D cube defined by eight RGB color points representing the eight vertices of the 3D cube is stored. Each of the eight points represents one of the colors: red, yellow, white, magenta, blue, black, green and cyan. In addition, each of the eight points represents the difference between the capacity of a display and the color standard. The 3D cube is divided into six tetrahedrons and the tetrahedron corresponding to an input RGB pixel is selected. A 3×3 matrix based on the vertices of the selected tetrahedron is calculated. The 3×3 matrix is then multiplied by the components of the input RGB pixel to produce an output RGB pixel conforming to the color standard.

Abstract: A system includes a signal reconstruction controller (110) electrically coupled to at least one analog-to-digital converter (ADC) (112) and to a phase adjustable clock source (108). A sampling clock signal (116) is electrically coupled from the clock source (108) to the at least one ADC (112). The at least one ADC (112) samples an electronic signal according to the sampling clock signal (116) to provide a digital representation of the electronic signal. The controller (110) samples data from the ADC (112) at different sampling points in the electronic signal and determines the edges (140) of the electronic signal and the noisy samples (142, 144) that are away from the edges (140) of the electronic signal. By finding the least noisy sample (146, 148) that is away from the edges (140) of the electronic signal the controller (110) adjusts the phase of a sampling signal clock (116) to a sampling point that is the most reliable to sample the electronic signal to provide a digital representation thereof.

Abstract: Channel coupled feedback- technology for implementing many analog and digital signal processing functions in a single-polysilicon digital IC fabrication process is described. Field effect transistors are constructed having a common channel and the substrate regions of the field effect transistors in the channel are electronically connected. Thus, a fixed amount of charge can freely move within the channel in response to the application of the signal to be processed. By sensing the charge transferred within the channel when the input signal is applied, many signal processing functions are possible. Fixed-gain amplifiers, offset compensated amplifiers, integrators, differentiators, analog-to-digital converters, digital-to-analog converters, switchable gain amplifiers, automatic gain control systems, and linear transform computation circuits are constructed entirely with field effect transistors, eliminating the need for passive components for most signal processing functions.

Abstract: A novel electronic apparatus for driving passive x-y addressed liquid crystal displays (LCDs) and having improved display performance is disclosed and claimed. This apparatus is comprised of row driving integrated circuits capable of driving row lines of the LCD with a pattern of voltages corresponding to the basis vectors of a linear transform matrix. Column driver circuits containing analog CMOS pixel memory store video information and compute the linear transform of the pixel matrix. High voltage amplifier circuits to drive the column lines with voltages corresponding to the linear transform of the pixel matrix columns can be monolithically integrated with the transform computation circuitry. The LCD screen inherently performs the inverse transform and displays the desired pixel matrix. The speed and contrast of the LCD are improved, allowing the display of video rate images on passive LCD screens.

Abstract: Novel high voltage electronic amplifiers that are capable of being monolithically integrated using low voltage semiconductor fabrication processes are described and claimed. A cascade of low voltage current mirrors is described that can act as a high voltage amplifier output circuit. A transconductor and level shift circuit is also described that can be employed in the high voltage amplifier output circuit. A high voltage current source is described and is constructed from the series combination of a low voltage transistor and a parasitic field oxide transistor. Additionally, a differential amplifier having bias-current shunting transistors is described that can be used to limit quiescent current from the output power supply of the high voltage amplifiers.

Abstract: Novel high voltage amplifiers that are capable of being monolithically integrated using low voltage semiconductor fabrication processes are described and claimed. A cascade of low voltage current mirrors is described that can act as a high voltage amplifier output circuit. A high voltage current source circuit also is described and is constructed from the series combination of a low voltage transistor and a parasitic field oxide transistor. Additionally, a differential amplifier having bias current shunting transistors is described that can be used to limit quiescent current from the power supply of the high voltage amplifiers.