Abstract: A synapse for neural network applications providing four quadrant feed-forward and feed-back modes in addition to an outer-product learning capability allowing learning in-situ. The invention, in its preferred embodiment, utilizes a novel two-transistor implementation which permits each synapse to be built in an integrated circuit chip surface area of only 20 by 20 micrometers. One of the two transistors at each synapse of the present invention comprises a floating gate structure composed of a floating gate electrode and a control electrode which permits learning upon application of incident ultraviolet light. During ultraviolet light application, a floating gate electrode voltage may be altered to modify the weight of each synapse in accordance with preselected criteria, based upon the input and output weight change vector elements corresponding to that particular matrix element.

Abstract: An adjustable CCD gate structure utilizing ultra-violet light activated floating gates, wherein a floating polysilicon gate is used between a CCD electrode and the underlying substrate to provide a fixed voltage bias to the CCD gate during the manufacturing process thereof The floating gate is programmed with a desired voltage bias during the application of ultra-violet light and is thereafter fixed at that adjusted level, upon the removal of the ultra-violet light.

Abstract: A charge domain bit serial vector matrix multiplier for real time signal processing of mixed digital/analog signals for implementing opto-electronic neural networks and other signal processing functions. A combination of CCD and DCSD arrays permits vector/matrix multiplication with better than 10.sup.11 multiply accumulates per second on a one square centimeter chip. The CCD array portion of the invention is used to load and move charge packets into the DCSD array for processing therein. The CCD array is also used to empty the matrix of unwanted charge. The DCSD array is designed to store a plurality of charge packets representing the respective matrix values such as the synaptic interaction matrix of a neural network. The vector multiplicand may be applied in bit serial format. The row or sensor lines of the DCSD array are used to accumulate the results of the multiply operation.

Abstract: A novel display screen structure and method of manufacturing such screens for use, for example, in large screen television displays. The process of the present invention is one which can be accomplished with no new materials, no critical geometric requirements such as critical separations and alignments and only low voltage drivers. The combination of these features results in a technology which can be easily scaled to large sizes to provide relatively low-cost large screens for televisions. An important step in a first embodiment of the present invention is the alignment of a large plurality of columnar-shaped light emitting diode slivers in an uncured optical epoxy by applying an electric field through a mixture of such slivers and epoxy and then curing the epoxy to effectively fix the light emitting diode slivers in that aligned configuration. In a second embodiment, the LED slivers are mixed with molten glass which is formed into elongated glass fibers.

Abstract: A novel display screen structure and method of manufacturing such screens for use, for example, in large screen television displays. The process of the present invention is one which can be accomplished with no new materials, no critical geometric requirements such as critical separations and alignments and only low voltage drivers. The combination of these features results in a technology which can be easily scaled to large sizes to provide relatively low-cost large screens for televisions. An important step in the disclosed embodiment of the present invention is the alignment of a large plurality of columnar-shaped light emitting diode slivers in an uncured optical epoxy by applying an electric field through a mixture of such slivers and epoxy and then curing the epoxy to effectively fix the light emitting diode slivers in that aligned configuration.

Abstract: Several embodiments of neural processors implemented on a VLSI circuit chip are disclosed, all of which are capable of entering a matrix T into an array of photosensitive devices which may be charge coupled or charge injection devices (CCD or CID). Using CCD's to receive and store the synapses of the matrix T from a spatial light modulator, or other optical means of projecting an array of pixels, semiparallel synchronous operation is achieved. Using CID's, full parallel synchronous operation is achieved. And using phototransistors to receive the array of pixels, full parallel and asynchronous operation is achieved. In the latter case, the source of the pixel matrix must provide the memory necessary for the matrix T. In the other cases, the source of the pixel matrix may be turned off after the matrix T has been entered and stored by the CCD's or CID's.