Abstract: An ultrasonic imaging system is described in which a column-row-parallel architecture is provided at the circuit level of an ultrasonic transceiver. The ultrasonic imaging system can include a N×M array of transducer elements and a plurality of transceiver circuits where each transceiver circuit is connected to a corresponding one transducer element of the N×M array of transducer elements. A shared pulser gate driver and a shared VGA is provided for each row and column. Selection logic includes row select, column select, and per-element bit select. Through the column-row-parallel architecture, a variety of aperture configurations can be achieved.

Abstract: Buffered body return receiver configurations are described. An amplifier for a receiver can be connected to two electrodes such that one of the two electrodes is connected to a non-inverting input of the amplifier and a second of the two electrodes is a driven node by being connected to both the inverting input of the amplifier and the output of the amplifier. The amplifier may be connected as a fully differential amplifier, a single-ended differential amplifier, a buffer, or an amplifier with a gain greater than 1, while still enabling improved channel gains with reduced power consumption at the transmitter from the signal source. The buffered body return receiver is suitable for scenarios in which a signal source is electrically independent of the power supply of the receiver's amplifier.

Abstract: A method and monitor for monitoring vital signs. In one embodiment, the vital signs monitor includes a housing sized and shaped for fitting adjacent the ear of a wearer and an electronic module for measuring vital signs. The electronic module for measuring vital signs is located within the housing and includes a plurality of vital signs sensing modules in communication with a processor. The plurality of sensing modules includes at least two of the modules selected from the group of a ballistocardiographic (BCG) module, a photoplethysmographic (PPG) module, an accelerometer module, a temperature measurement module, and an electrocardiographic (ECG) module. In one embodiment, the processor calculates additional vital signs in response to signals from the plurality of vital signs sensing modules.

Abstract: A circuit for expanding a dynamic range. In one embodiment, the circuit includes: a transducer generating a signal current on an output terminal in response to a physical quantity, the signal current comprising an AC current and a DC current; a dynamic range enhancement circuit having a digital control signal input terminal and producing a variable opposition current in response to a digital signal applied to the digital control signal input terminal; an amplifier; an analog to digital converter in electrical communication with the amplifier; and a digital feedback circuit in communication with the output terminal of the analog to digital converter and in electrical communication with the digital control signal input terminal of the dynamic range enhancement circuit, wherein the opposition current from the dynamic range enhancement circuit is set substantially equal to the DC current portion of the signal current from the transducer.

Abstract: A circuit for expanding a dynamic range. In one embodiment, the circuit includes: a transducer generating a signal current on an output terminal in response to a physical quantity, the signal current comprising an AC current and a DC current; a dynamic range enhancement circuit having a digital control signal input terminal and producing a variable opposition current in response to a digital signal applied to the digital control signal input terminal; an amplifier; an analog to digital converter in electrical communication with the amplifier; and a digital feedback circuit in communication with the output terminal of the analog to digital converter and in electrical communication with the digital control signal input terminal of the dynamic range enhancement circuit, wherein the opposition current from the dynamic range enhancement circuit is set substantially equal to the DC current portion of the signal current from the transducer.

Abstract: Buffered body return receiver configurations are described. An amplifier for a receiver can be connected to two electrodes such that one of the two electrodes is connected to a non-inverting input of the amplifier and a second of the two electrodes is a driven node by being connected to both the inverting input of the amplifier and the output of the amplifier. The amplifier may be connected as a fully differential amplifier, a single-ended differential amplifier, a buffer, or an amplifier with a gain greater than 1, while still enabling improved channel gains with reduced power consumption at the transmitter from the signal source. The buffered body return receiver is suitable for scenarios in which a signal source is electrically independent of the power supply of the receiver's amplifier.

Abstract: A circuit and method for long term electrocardiogram (ECG) monitoring is implemented with the goal of reducing power consumption, battery size, and consequently device size. In one embodiment, the integrated circuit includes an amplifier cell having a plurality of input terminals and an output terminal; a QRS amplifier cell in communication with the output of the amplifier cell; a baseline amplifier cell in communication with the output of the amplifier cell; a comparator cell having a first input terminal in communication with the output terminal of the QRS amplifier cell; and a VDC cell having an input in communication with the output of the baseline amplifier cell and an output in communication with the second input terminal of the comparator cell, wherein the comparator cell generates an output pulse in response to the output signal from the amplifier cell and the output signal from the baseline amplifier cell.

Abstract: An ultrasonic imaging system is described in which a column-row-parallel architecture is provided at the circuit level of an ultrasonic transceiver. The ultrasonic imaging system can include a N×M array of transducer elements and a plurality of transceiver circuits where each transceiver circuit is connected to a corresponding one transducer element of the N×M array of transducer elements. A shared pulser gate driver and a shared VGA is provided for each row and column. Selection logic includes row select, column select, and per-element bit select. Through the column-row-parallel architecture, a variety of aperture configurations can be achieved.

Abstract: A circuit and method for long term electrocardiogram (ECG) monitoring is implemented with the goal of reducing power consumption, battery size, and consequently device size. In one embodiment, the integrated circuit includes an amplifier cell having a plurality of input terminals and an output terminal; a QRS amplifier cell in communication with the output of the amplifier cell; a baseline amplifier cell in communication with the output of the amplifier cell; a comparator cell having a first input terminal in communication with the output terminal of the QRS amplifier cell; and a VDC cell having an input in communication with the output of the baseline amplifier cell and an output in communication with the second input terminal of the comparator cell, wherein the comparator cell generates an output pulse in response to the output signal from the amplifier cell and the output signal from the baseline amplifier cell.

Abstract: A physiological monitor for measuring a pulsatile motion signal (MoCG) that is delayed from, but at the same rate as, the heartbeat of a user. In one embodiment, the system includes a housing configured to be worn on the body of a user; at least one MoCG sensor, within the housing, that measures a pulsatile motion signal (MoCG) that is delayed from, but at the same rate as, the heartbeat of the user; and at least one data processor that calculates, solely based on an output of the at least one MoCG sensor, at least one of (i) heart rate (HR) and activity level for the user, and (ii) respiratory rate (RR), stroke volume (SV), and cardiac output (CO) for the user. In another embodiment, the at least one data processor is within the housing.

Abstract: A method and monitor for monitoring vital signs. In one embodiment, the vital signs monitor includes a housing sized and shaped for fitting adjacent the ear of a wearer and an electronic module for measuring vital signs. The electronic module for measuring vital signs is located within the housing and includes a plurality of vital signs sensing modules in communication with a processor. The plurality of sensing modules includes at least two of the modules selected from the group of a ballistocardiographic (BCG) module, a photoplethysmographic (PPG) module, an accelerometer module, a temperature measurement module, and an electrocardiographic (ECG) module. In one embodiment, the processor calculates additional vital signs in response to signals from the plurality of vital signs sensing modules.

Abstract: A system and method process non-linear image data, still or video, from a digital imager. Noise generated by analog-to-digital converters is filtered from a pixel of digital image data. Moreover, the effects of single pixel defects in the imager are eliminated by clamping a predetermined pixel of image data within the window when the value of the predetermined pixel is greater than a maximum value of the image data of neighboring pixels or less than a minimum value of the image data of neighboring pixels. Ripples in image data are reduced by eliminating the effects of single pixel defects before filtering for crosstalk caused by electrical crosstalk between sensor elements in an imager. Dark current is removed from image data generated by an imager by subtracting a fraction of a determined dark current value from all image data generated by the imager to compensate for nonlinearities in dark current across the imager.

Abstract: Described is a switched capacitor circuit for performing an analog circuit function. Unlike conventional switched capacitor circuits employing operational amplifiers, the switched capacitor circuit uses a comparator and does not require direct feedback between the input and output of the comparator. The switched capacitor circuit includes a first and a second switched capacitance network, a comparator and a current source. The first switched capacitance network has an input terminal to receive a circuit input voltage during a first phase. The comparator has an input terminal in communication with the first switched capacitance network and an output terminal in communication with the second switched capacitance network through a switched terminal. The current source communicates with the switched capacitance networks and supplies a current to charge the networks during a second phase. The circuit can be used, for example, to provide high gain amplification in integrated circuits.

Abstract: The imager system of the invention, provided in a semiconductor substrate, includes a plurality of photosensitive, charge integrating pixels that are arranged in rows and columns of a pixel array for capturing illumination of a scene to be imaged. Each pixel includes a photogenerated charge accumulation region of the semiconductor substrate and a sense node at which an electrical signal, indicative of pixel charge accumulation, can be measured without discharging the accumulation region. Pixel access control circuitry is connected to pixel array rows and columns to deliver pixel access signals generated by the access control circuitry for independently accessing a selected pixel in the array. An input interface circuit is connected to accept a dynamic range specification input for the array pixels.

Abstract: An image input section and a signal processing section are provided. The image input section includes an array of pixel in which a plurality of pixels having a CMOS type photoelectric converting element for converting incident light to an electric signal are arranged in a matrix, and a data read-out circuit having the same number of A/D converters as the number of the pixels arranged in one row of the array of pixel and serving to convert the analog signal converted by the pixels into a digital signal and to output the digital signal. The signal processing section includes plurality of processors. Each of the processors includes a plurality of processing elements (PE) provided on the A/D converter provided in the data read-out circuit by one to one. Moreover, a plurality of PEs provided in each of the processors have the same data processing function in the same processor. Furthermore, the PEs in the processor carry out a signal processing in parallel in response to an instruction.

Abstract: There is provided an imaging system including a MOS pixel array having a number, r, of rows of pixels. Each pixel of the array includes a light detecting element, a reset node connected to the light detecting element for controlling dissipation of photogenerated charge produced by the light detecting element, and a sense node connected to the light detecting element for measuring photogenerated charge produced by the light detecting element. A charge control voltage generation circuit is provided, having a topology for producing a plurality of charge control voltages selected to control dissipation of photogenerated charge produced by the light detecting element, in accordance with a corresponding pixel transfer function. A switch circuit is connected to the voltage generation circuit and to the pixel array to apply voltages produced by the charge control voltage generation circuit to reset nodes of pixels.

Abstract: An image input section and a signal processing section are provided. The image input section includes an array of pixel in which a plurality of pixels having a CMOS type photoelectric converting element for converting incident light to an electric signal are arranged in a matrix, and a data read-out circuit having the same number of A/D converters as the number of the pixels arranged in one row of the array of pixel and serving to convert the analog signal converted by the pixels into a digital signal and to output the digital signal. The signal processing section includes plurality of processors. Each of the processors includes a plurality of processing elements (PE) provided on the A/D converter provided in the data read-out circuit by one to one. Moreover, a plurality of PEs provided in each of the processors have the same data processing function in the same processor. Furthermore, the PEs in the processor carry out a signal processing in parallel in response to an instruction.

Abstract: An image input section and a signal processing section are provided. The image input section includes an array of pixel in which a plurality of pixels having a CMOS type photoelectric converting element for converting incident light to an electric signal are arranged in a matrix, and a data read-out circuit having the same number of A/D converters as the number of the pixels arranged in one row of the array of pixel and serving to convert the analog signal converted by the pixels into a digital signal and to output the digital signal. The signal processing section includes plurality of processors. Each of the processors includes a plurality of processing elements (PE) provided on the A/D converter provided in the data read-out circuit by one to one. Moreover, a plurality of PEs provided in each of the processors have the same data processing function in the same processor. Furthermore, the PEs in the processor carry out a signal processing in parallel in response to an instruction.

Abstract: There is provided an imaging system including a MOS pixel array having a number, r, of rows of pixels. Each pixel of the array includes a light detecting element, a reset node connected to the light detecting element for controlling dissipation of photogenerated charge produced by the light detecting element, and a sense node connected to the light detecting element for measuring photogenerated charge produced by the light detecting element. A charge control voltage generation circuit is provided, having a topology for producing a plurality of charge control voltages selected to control dissipation of photogenerated charge produced by the light detecting element, in accordance with a corresponding pixel transfer function. A switch circuit is connected to the voltage generation circuit and to the pixel array to apply voltages produced by the charge control voltage generation circuit to reset nodes of pixels.

Abstract: A digital compensation filtering technique is provided that enables indirect phase locked loop modulation with a digital modulation data stream having a bandwidth that exceeds, perhaps by an order of magnitude, the bandwidth characteristic of the phase locked loop. A modulation data receiver is provided for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency characteristic of the phase locked loop frequency response. A digital processor is coupled to the modulation data receiver for digitally processing the input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency.