Patents by Inventor Charles Koburger
Charles Koburger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070108473Abstract: An optical sensor and method for forming the same. The optical sensor structure includes (a) a semiconductor substrate, (b) first, second, third, fourth, fifth, and sixth electrodes and (c) first, second, and third semiconducting regions. The first and fourth electrodes are at a first depth. The second and fifth electrodes are at a second depth. The third and sixth electrodes are at a third depth. The first depth is greater than the second depth, and the second depth is greater than the third depth. The first, second, and third semiconducting regions are disposed between and in contact with the first and fourth electrodes, second and fifth electrodes, and third and sixth electrodes, respectively. The first, second, and third semiconducting regions are in contact with each other.Type: ApplicationFiled: November 15, 2005Publication date: May 17, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20070105319Abstract: A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are added between two adjacent design normal regions of the M design normal regions, wherein N is a positive integer. Next, an actual structure is provided that includes (i) an actual substrate corresponding to the design substrate, (ii) a to-be-etched layer on the actual substrate, and (iii) a memory layer on the to-be-etched layer. Next, an edge printing process is performed on the memory layer so as to form (a) M normal memory portions aligned with the M design normal regions and (b) N sacrificial memory portions aligned with the N design sacrificial regions.Type: ApplicationFiled: November 4, 2005Publication date: May 10, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20070102766Abstract: A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.Type: ApplicationFiled: November 4, 2005Publication date: May 10, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, William Tonti
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Publication number: 20070096263Abstract: A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.Type: ApplicationFiled: November 3, 2005Publication date: May 3, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20070099416Abstract: Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.Type: ApplicationFiled: October 31, 2005Publication date: May 3, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Larry Nesbit
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Publication number: 20070085156Abstract: Acceleration and voltage measurement devices and methods of fabricating acceleration and voltage measurement devices. The acceleration and voltage measurement devices including an electrically conductive plate on a top surface of a first insulating layer; a second insulating layer on a top surface of the conductive plate, the top surface of the plate exposed in an opening in the second insulating layer; conductive nanotubes suspended across the opening, and electrically conductive contacts to said nanotubes.Type: ApplicationFiled: October 13, 2005Publication date: April 19, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Leah Pastel
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Publication number: 20070076179Abstract: An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.Type: ApplicationFiled: September 30, 2005Publication date: April 5, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven Holmes, Toshiharu Furukawa, Charles Koburger III, Naim Moumen
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Publication number: 20070063392Abstract: An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.Type: ApplicationFiled: September 22, 2005Publication date: March 22, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles Koburger III, Steven Holmes, David Horak, Kurt Kimmel, Karen Petrillo, Christopher Robinson
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Publication number: 20070066009Abstract: A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces of the structure. Then, portions of the conformal protective layer are removed so as to expose the capping region to the surrounding ambient without exposing the memory region to the surrounding ambient. Then, the capping region is removed so as to expose the positioning region to the surrounding ambient. Then, the positioning region is removed so as to expose the memory region to the surrounding ambient. Then, the memory region is directionally etched with remaining portions of the conformal protection layer serving as a blocking mask.Type: ApplicationFiled: September 19, 2005Publication date: March 22, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Kirk Peterson
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Publication number: 20070059891Abstract: Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.Type: ApplicationFiled: September 14, 2005Publication date: March 15, 2007Applicant: International Business Machines CorporationInventors: Toshiharu Furukawa, David Horak, Charles Koburger, Qiqing Ouyang
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Publication number: 20070057323Abstract: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.Type: ApplicationFiled: September 12, 2005Publication date: March 15, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Jack Mandelman
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Publication number: 20070051237Abstract: An air particle precipitator and a method of air filtration comprise a housing unit; a first conductor in the housing unit; a second conductor in the housing unit; and a carbon nanotube grown on the second conductor. Preferably, the first conductor is positioned opposite to the second conductor. The air particle precipitator further comprises an electric field source adapted to apply an electric field to the housing unit. Moreover, the carbon nanotube is adapted to ionize gas in the housing unit, wherein the ionized gas charges gas particulates located in the housing unit, and wherein the first conductor is adapted to trap the charged gas particulates. The air particle precipitator may further comprise a metal layer over the carbon nanotube.Type: ApplicationFiled: July 27, 2005Publication date: March 8, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20070048879Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.Type: ApplicationFiled: October 25, 2006Publication date: March 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Peter Mitchell
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Publication number: 20070023839Abstract: A fin field effect transistor (FinFET) gate comprises a semiconductor wafer; a gate dielectric layer over the semiconductor wafer; a conductive material on the gate dielectric layer; an activated carbon nanotube on a surface of the conductive material; and a plated metal layer on the activated carbon nanotube. Preferably, the carbon nanotube is on a sidewall of the conductive material. The conductive material comprises a first metal layer over the gate dielectric layer, wherein the first metal layer acts as a catalyst for growing the carbon nanotube, wherein the first metal layer is preferably in a range of 1-10 nm in thickness. The semiconductor wafer may comprise a silicon on insulator wafer. The FinFET gate may further comprise a second metal layer disposed between the first metal layer and the gate dielectric layer.Type: ApplicationFiled: July 27, 2005Publication date: February 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20070025138Abstract: Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.Type: ApplicationFiled: July 26, 2005Publication date: February 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20070021293Abstract: A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.Type: ApplicationFiled: July 25, 2005Publication date: January 25, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Mark Masters
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Publication number: 20060292861Abstract: Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.Type: ApplicationFiled: July 20, 2006Publication date: December 28, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, David Horak, Charles Koburger, Mark Masters, Peter Mitchell, Stanislav Polonsky
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Publication number: 20060267086Abstract: Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.Type: ApplicationFiled: May 31, 2005Publication date: November 30, 2006Applicant: International Business Machines CorporationInventors: Toshijaru Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Chung Lam, Gerhard Meijer
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Publication number: 20060228835Abstract: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface ; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.Type: ApplicationFiled: April 6, 2005Publication date: October 12, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger
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Publication number: 20060226480Abstract: The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be reduced and relatively long and high temperature annealing process steps may be shortened or eliminated. This simplification may be achieved if, after oxygen implant, the wafer structure is sent to pad formation, and masking and etching. After the etching, annealing or oxidation process steps may be performed to create the SOI wafer.Type: ApplicationFiled: April 6, 2005Publication date: October 12, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Toshiharu Furukawa, Mark Hakey, Steven Holmes, David Horak, Charles Koburger, Larry Nesbit